Semiconductor integrated circuit device
View Patent ↗A semiconductor integrated circuit device capable of suppressing variations in transistor characteristics due to the well proximity effect is provided. Standard cell rows are arranged in a vertical direction, each standard cell row including standard cells arranged in a horizontal direction. In the standard cell rows, positions of the N well and the P region in the vertical direction are switched every other row. Adjacent standard cell rows share the P region or the N well. A distance from a PMOS transistor located at an end of a standard cell row to an end of an N well is greater than or equal to a width of an N well shared by standard cell rows.
1. A semiconductor integrated circuit device comprising:
a circuit block including a plurality of standard cell rows arranged in a vertical direction, each standard cell row including standard cells arranged in a horizontal direction,
wherein each of the standard cell rows includes an N well and a P region extending in the horizontal direction and adjacent to each other in the vertical direction,
each of the standard cells has a PMOS transistor formed in the N well and an NMOS transistor formed in the P region,
in the standard cell rows, positions of the N well and the P region in the vertical direction are switched every other row, the first and second standard cell rows share the P region, and the second and third standard cell rows share the N well,
in at least one of the standard cell rows, a distance from a PMOS transistor located at least one end thereof to an end closer to the PMOS transistor in the horizontal direction of the N well is greater than or equal to a shared-N well width which is a width in the vertical direction of the N well shared by the second and third standard cell rows.
2. The semiconductor integrated circuit device of claim 1 , wherein
in the at least one standard cell row, each of the standard cells has a distance in the horizontal direction from the PMOS transistor to an end of the N well, the distance being greater than or equal to the shared-N well width.
3. The semiconductor integrated circuit device of claim 1 , wherein
in the at least one standard cell row, a dummy cell having an N well is arranged closer to the outside than the standard cell having the PMOS transistor.
4. The semiconductor integrated circuit device of claim 3 , wherein
the dummy cell is a standard cell which does not share an input/output with any other standard cells.
5. The semiconductor integrated circuit device of claim 3 , wherein
the dummy cell includes an inter-powerline capacitance element, a diode element, a dummy gate which is not connected to any other elements, or a dummy wire which is not connected to any other elements.
6. The semiconductor integrated circuit device of claim 1 , wherein
a width in the vertical direction of the N well in the first standard cell row is greater than or equal to the shared-N well width.
7. The semiconductor integrated circuit device of claim 1 , wherein
the P region is a P well.
8. A semiconductor integrated circuit device comprising:
a first circuit block and a second circuit block each including a plurality of standard cell rows arranged in a vertical direction, each standard cell row including standard cells arranged in a horizontal direction,
wherein each of the standard cell rows includes an N well and a P region extending in the horizontal direction and adjacent to each other in the vertical direction,
each of the standard cells has a PMOS transistor formed in the N well and an NMOS transistor formed in the P region,
in the standard cell rows of each of the first and second circuit block, positions of the N well and the P region in the vertical direction are switched every other row, the first and second standard cell rows share the P region, and the second and third standard cell rows share the N well,
a height in the vertical direction of the standard cell in the second circuit block is greater than a height in the vertical direction of the standard cell in the first circuit block,
in at least one of the standard cell rows in the second circuit block, a distance from a PMOS transistor located at least one end thereof to an end closer to the PMOS transistor in the horizontal direction of the N well is greater than or equal to a width in the vertical direction of the N well shared by the second and third standard cell rows in the first circuit block.
9. A semiconductor integrated circuit device comprising:
a circuit block including a plurality of standard cell rows arranged in a vertical direction, each standard cell row including standard cells arranged in a horizontal direction,
wherein each of the standard cell rows includes an N well and a P region extending in the horizontal direction and adjacent to each other in the vertical direction,
each of the standard cells has a PMOS transistor formed in the N well and an NMOS transistor formed in the P region,
in the standard cell rows, positions of the N well and the P region in the vertical direction are switched every other row, the first and second standard cell rows share the P region, and the second and third standard cell rows share the N well,
a width in the vertical direction of the N well in the first standard cell row is greater than or equal to a shared-N well width which is a width in the vertical direction of the N well shared by the second and third standard cell rows, and
each of the standard cells has a width in the vertical direction of the N well greater than or equal to the shared-N well width.
10. A semiconductor integrated circuit device comprising:
a circuit block including a plurality of standard cell rows arranged in a vertical direction, each standard cell row including standard cells arranged in a horizontal direction,
wherein each of the standard cell rows includes an N well and a P region extending in the horizontal direction and adjacent to each other in the vertical direction,
each of the standard cells has a PMOS transistor formed in the N well and an NMOS transistor formed in the P region,
in the standard cell rows, positions of the N well and the P region in the vertical direction are switched every other row, the first and second standard cell rows share the P region, and the second and third standard cell rows share the N well,
a dummy cell row having dummy cells arranged in the horizontal direction, each dummy cell having an N well, is arranged closer to the outside than the first standard cell row with the N well being shared with the dummy cell row and the first standard cell row, and
a width in the vertical direction of the N well shared by the first standard cell row and the dummy cell row is greater than or equal to a shared-N well width which is a width in the vertical direction of the N well shared by the second and third standard cell rows.
11. The semiconductor integrated circuit device of claim 10 , wherein
the dummy cell is a standard cell which does not share an input/output with any other standard cells.
12. The semiconductor integrated circuit device of claim 10 , wherein
the dummy cell includes an inter-powerline capacitance element, a diode element, a dummy gate which is not connected to any other elements, or a dummy wire which is not connected to any other elements.
13. The semiconductor integrated circuit device of claim 10 , wherein
the dummy cell does not have a P region.
14. A semiconductor integrated circuit device comprising:
a circuit block including a plurality of standard cell rows arranged in a vertical direction, each standard cell row including standard cells arranged in a horizontal direction,
wherein each of the standard cell rows includes an N well and a P well extending in the horizontal direction and adjacent to each other in the vertical direction,
each of the standard cells has a PMOS transistor formed in the N well and an NMOS transistor formed in the P well,
in the standard cell rows, positions of the N well and the P well in the vertical direction are switched every other row, the first and second standard cell rows share the N well, and the second and third standard cell rows share the P well, and
a width in the vertical direction of the P well in the first standard cell row is greater than or equal to a width in the vertical direction of the P well shared by the second and third standard cell rows.
15. The semiconductor integrated circuit device of claim 14 , wherein
a dummy cell row having dummy cells arranged in the horizontal direction is arranged closer to the outside than the first standard cell row with the P well being shared with the dummy cell row and the first standard cell row.
16. A semiconductor integrated circuit device comprising:
a circuit block including a plurality of standard cell rows arranged in a vertical direction, each standard cell row including standard cells arranged in a horizontal direction,
wherein each of the standard cell rows includes an N well and a P well extending in the horizontal direction and adjacent to each other in the vertical direction,
each of the standard cells has a PMOS transistor formed in the N well and an NMOS transistor formed in the P well,
in the standard cell rows, positions of the N well and the P well in the vertical direction are switched every other row, the first and second standard cell rows share the N well, and the second and third standard cell rows share the P well, and
in at least one of the standard cell rows, a distance from an NMOS transistor located at least one end thereof to an end closer to the NMOS transistor in the horizontal direction of the P well is greater than or equal to a shared-P well width which is a width in the vertical direction of the P well shared by the second and third standard cell rows.
17. The semiconductor integrated circuit device of claim 16 , wherein
the N well and the P well possessed by each of the standard cell rows are formed on a triple well which is an N well.
18. The semiconductor integrated circuit device of claim 16 , wherein
in the at least one standard cell row, each of the standard cells has a distance in the horizontal direction from the NMOS transistor to an end of the P well, the distance being greater than or equal to the shared-P well width.
19. The semiconductor integrated circuit device of claim 16 , wherein
in the at least one standard cell row, a dummy cell having a P well is arranged closer to the outside than the standard cell having the PMOS transistor.
20. The semiconductor integrated circuit device of claim 19 , wherein
the dummy cell is a standard cell which does not share an input/output with any other standard cells.
21. The semiconductor integrated circuit device of claim 19 , wherein
the dummy cell includes an inter-powerline capacitance element, a diode element, a dummy gate which is not connected to any other elements, or a dummy wire which is not connected to any other elements.
22. The semiconductor integrated circuit device of claim 16 , wherein
a width in the vertical direction of the P well in the first standard cell row is greater than or equal to the shared-P well width.
23. A semiconductor integrated circuit device comprising:
a first circuit block and a second circuit block each including a plurality of standard cell rows arranged in a vertical direction, each standard cell row including standard cells arranged in a horizontal direction,
wherein each of the standard cell rows includes an N well and a P well extending in the horizontal direction and adjacent to each other in the vertical direction,
each of the standard cells has a PMOS transistor formed in the N well and an NMOS transistor formed in the P well,
in the standard cell rows of each of the first and second circuit block, positions of the N well and the P well in the vertical direction are switched every other row, the first and second standard cell rows share the N well, and the second and third standard cell rows share the P well,
a height in the vertical direction of the standard cell in the second circuit block is greater than a height in the vertical direction of the standard cell in the first circuit block,
in at least one of the standard cell rows in the second circuit block, a distance from an NMOS transistor located at least one end thereof to an end closer to the NMOS transistor in the horizontal direction of the P well is greater than or equal to a width in the vertical direction of the P well shared by the second and third standard cell rows in the first circuit block.
24. A semiconductor integrated circuit device comprising:
a circuit block including a plurality of standard cell rows arranged in a vertical direction, each standard cell row including standard cells arranged in a horizontal direction,
wherein each of the standard cell rows includes an N well and a P well extending in the horizontal direction and adjacent to each other in the vertical direction,
each of the standard cells has a PMOS transistor formed in the N well and an NMOS transistor formed in the P well,
in the standard cell rows, positions of the N well and the P well in the vertical direction are switched every other row, the first and second standard cell rows share the N well, and the second and third standard cell rows share the P well,
a width in the vertical direction of the P well in the first standard cell row is greater than or equal to a shared-P well width which is a width in the vertical direction of the P well shared by the second and third standard cell rows, and
each of the standard cells has a width in the vertical direction of the P well greater than or equal to the shared-P well width.
25. A semiconductor integrated circuit device comprising:
a circuit block including a plurality of standard cell rows arranged in a vertical direction, each standard cell row including standard cells arranged in a horizontal direction,
wherein each of the standard cell rows includes an N well and a P well extending in the horizontal direction and adjacent to each other in the vertical direction,
each of the standard cells has a PMOS transistor formed in the N well and an NMOS transistor formed in the P well,
in the standard cell rows, positions of the N well and the P well in the vertical direction are switched every other row, the first and second standard cell rows share the N well, and the second and third standard cell rows share the P well,
a dummy cell row having dummy cells arranged in the horizontal direction, each dummy cell having a P well, is arranged closer to the outside than the first standard cell row with the P well being shared with the dummy cell row and the first standard cell row, and
a width in the vertical direction of the P well shared by the first standard cell row and the dummy cell row is greater than or equal to a shared-P well width which is a width in the vertical direction of the P well shared by the second and third standard cell rows.
26. The semiconductor integrated circuit device of claim 25 , wherein
the dummy cell is a standard cell which does not share an input/output with any other standard cells.
27. The semiconductor integrated circuit device of claim 25 , wherein
the dummy cell includes an inter-powerline capacitance element, a diode element, a dummy gate which is not connected to any other elements, or a dummy wire which is not connected to any other elements.
28. The semiconductor integrated circuit device of claim 25 , wherein
the dummy cell does not have an N well.
29. A semiconductor integrated circuit device comprising:
a circuit block including a plurality of standard cell rows arranged in a vertical direction, each standard cell row including standard cells arranged in a horizontal direction,
wherein each of the standard cell rows includes an N well and a P well extending in the horizontal direction and adjacent to each other in the vertical direction,
the N well and the P well possessed by each of the standard cell rows are formed on a triple well which is an N well,
each of the standard cells has a PMOS transistor formed in the N well and an NMOS transistor formed in the P well,
in the standard cell rows, positions of the N well and the P well in the vertical direction are switched every other row, the first and second standard cell rows share the P well, and the second and third standard cell rows share the N well, and
a width in the vertical direction of an N well which is a combination of the N well of the first standard cell row and the triple-well formed outside the N well of the first standard cell row is greater than or equal to a width in the vertical direction of the N well shared by the second and third standard cell rows.