SEMICONDUCTOR DEVICE MANUFACTURING METHOD
A yielding percentage is calculated based on a first relationship, a probability distribution and a second relationship. The first relationship is a relationship between measurement values of a transfer pattern formed on a semiconductor substrate provided in the semiconductor device in the semiconductor lithographic process and number of sections on the semiconductor substrate where the measurement values are set. The probability distribution is a probability distribution showing variation of manufacturing parameters in the semiconductor lithographic process. The second relationship is a relationship between the manufacturing parameters and the measurement values.
1 . A method of manufacturing a semiconductor device the calculation of a yielding percentage variable due to the connection failure in wiring in a semiconductor lithographic process , wherein
the yielding percentage is calculated based on a first relationship, a probability distribution and a second relationship,
the first relationship is a relationship between measurement values of a transfer pattern formed on a semiconductor substrate provided in the semiconductor device in the semiconductor lithographic process and number of sections on the semiconductor substrate where the measurement values are set,
the probability distribution is a probability distribution showing variation of manufacturing parameters in the semiconductor lithographic process, and
the second relationship is a relationship between the manufacturing parameters and the measurement values.
2 . The method of manufacturing the semiconductor device as claimed in claim 1 , wherein
a function representing a relationship between the manufacturing parameters and the measurement values is further calculated.
3 . The method of manufacturing the semiconductor device as claimed in claim 1 , further including:
a step of setting a layout of the semiconductor device on the semiconductor substrate and then simulating the transfer pattern based on the set layout; and
a step of measuring the simulated transfer pattern and detecting a section of the transfer pattern where a pattern width is narrower than a certain width previously set, wherein
the yielding percentage is calculated based on the function representing the relationship between the manufacturing parameters and the measurement values and the probability distribution showing the variation of the manufacturing parameters.
4 . The method of manufacturing the semiconductor device as claimed in claim 1 , wherein
the variability distribution is expressed by a normal distribution.
5 . The method of manufacturing the semiconductor device as claimed in claim 3 , wherein
a focus value in the semiconductor lithographic process is used as the manufacturing parameter, and the function is a function representing a relationship between the focus value and the measurement values.
6 . The method of manufacturing the semiconductor device as claimed in claim 3 , wherein
an exposure value in the semiconductor lithographic process is used as the manufacturing parameter, and the function is a function representing a relationship between the exposure value and the measurement values.
7 . The method of manufacturing the semiconductor device as claimed in claim 2 , wherein
a mask alignment value in the semiconductor lithographic process is used as the manufacturing parameter, and the function is a function representing a relationship between an area where a wiring pattern on the semiconductor substrate and contact holes on the semiconductor substrate overlap with each other and the mask alignment shift value.
8 . The method of manufacturing the semiconductor device as claimed in claim 5 , wherein
the probability distribution of the focus value is regarded as equal within a certain distance range from the detected section.
9 . The method of manufacturing the semiconductor device as claimed in claim 6 , wherein
the probability distribution of the exposure value is regarded as equal within a certain distance range from the detected section.
10 . The method of manufacturing the semiconductor device as claimed in claim 1 , wherein
the yielding percentage is calculated f or a part of cells in the semiconductor device.
11 . The method of manufacturing the semiconductor device as claimed in claim 3 , wherein
the certain width is set to a value smaller than a pattern width used to judge a wiring connection failure in the layout.
12 . The method of manufacturing the semiconductor device as claimed in claim 3 , wherein
the same function is set in the layouts having an equal shape.
13 . The method of manufacturing the semiconductor device as claimed in claim 3 , wherein
a plurality of layouts are generated with respect to the semiconductor integrated circuit, the yielding percentage is calculated in each of the plurality of layouts, and an optimum layout is selected based on comparison of the calculated yielding percentages.
14 . The method of manufacturing the semiconductor device as claimed in claim 3 , further including a step of calculating the yielding percentage resulting from a failure generated with a certain probability in a manufacturing process.