IP Library Patent Application 12063051
Patent Application
App. No. 12/063,051

FLAT DISPLAY

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Quick Facts
Patent No.
US None
App. No.
12/063,051
Abstract

Disclosed here is a flat display having a pair of glass substrates and a sealing member applied on the periphery of the glass substrates. The glass substrates are oppositely disposed to each other at intervals therebetween. The glass substrates contain silicon as a component, while the sealing member contains bismuth. A protection layer and an insulating layer as an intermediate layer, which has a silicon-content lower than the glass substrates, are formed on the interface between the glass substrates and the sealing member. The structure above reinforces bonding strength of the sealing section, providing a highly reliable flat display.

Claims (31)

1 . A flat display comprising:

a pair of silicon-contained glass substrates oppositely disposed at intervals therebetween; and

a bismuth-contained sealing member disposed on a periphery of the pair of glass substrates,

wherein, an intermediate layer whose silicon-content is lower than that of the glass substrate is disposed at an interface between the glass substrates and the sealing member.

2 . A flat display comprising:

a front substrate further including:

a glass substrate on which display electrodes are formed;

a dielectric layer disposed on the glass substrate so as to cover the display electrodes; and

a protection layer disposed on the dielectric layer; and

a back substrate disposed opposite to the front substrate, the back substrate further including:

a glass substrate to be paired with the glass substrate of the front substrate;

an data electrode disposed on the glass substrate; and

an insulating layer that covers the data electrodes; and

a bismuth-contained sealing member for sealing a periphery of the front substrate and the back substrate,

wherein, an intermediate layer whose silicon-content is lower than that of the glass substrates is disposed at an interface between the glass substrates and the sealing member.

3 . The flat display of claim 1 , wherein the intermediate layer has a thickness of at least 0.1 μm.

4 . The flat display of claim 1 , wherein the intermediate layer is formed on an entire surface of the glass substrates.

5 . The flat display of claim 1 wherein the intermediate layer is formed on the glass substrates so as to occupy at least 50% of an area where the sealing member is applied.

6 . The flat display of claim 1 , wherein the intermediate layer is made of a glass with a low melting point or a crystalline oxide film.

7 . The flat display of claim 1 , wherein the intermediate layer is made of a glass with a low melting point and has a silicon-content not greater than half of that of the glass substrates.

8 . The flat display of claim 1 , wherein the sealing member contains bismuth as a main component.

9 . The flat display of claim 1 , wherein the intermediate layer is formed on at least one of two interfaces between the sealing member and the pair of glass substrates.

10 . The flat display of claim 2 , wherein the intermediate layer is the dielectric layer or the protection layer of the front substrate.

11 . The flat display of claim 2 , wherein the intermediate layer is the insulating layer of the back substrate.

12 . The flat display of claim 2 , wherein the intermediate layer has a thickness of at least 0.1 μm.

13 . The flat display of claim 2 , wherein the intermediate layer is formed on an entire surface of the glass substrates.

14 . The flat display of claim 2 wherein the intermediate layer is formed on the glass substrates so as to occupy at least 50% of an area where the sealing member is applied.

15 . The flat display of claim 2 , wherein the intermediate layer is made of a glass with a low melting point or a crystalline oxide film.

16 . The flat display of claim 2 , wherein the intermediate layer is made of a glass with a low melting point and has a silicon-content not greater than half of that of the glass substrates.

17 . The flat display of claim 2 , wherein the sealing member contains bismuth as a main component.

18 . The flat display of claim 2 , wherein the intermediate layer is formed on at least one of two interfaces between the sealing member and the pair of glass substrates.

Assignments (2)
CHANGE OF NAME Recorded Nov 11, 2008
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 021818/0725 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 6, 2008
From: AKIYAMA, KOJI; NISHINAKA, MASAKI; MIYAZAKI, AKINOBU
To: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Reel/Frame 021058/0118 →