A PLL comprises a current-controlled oscillator ( 18 ) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source ( 28 ), and an initialization switch ( 26 ) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator ( 18 ) and the current source ( 28 ).
1. A PLL circuit comprising a loop filter for smoothing a current which is pushed and pulled in accordance with a phase difference between a reference clock signal and a feedback clock signal, a voltage-current converting circuit for converting an output voltage of the loop filter into a current, and a current-controlled oscillator for generating an output clock signal based on a current signal output from the voltage-current converting circuit, characterized by comprising:
a current source; and
an initialization switch which, when receiving an initialization signal, goes to a conductive state, and otherwise, goes to a non-conductive state, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator and the current source;
a reset switch which, when receiving a reset signal, goes to a conductive state, and otherwise, goes to a non-conductive state, the reset switch being provided between an input terminal of the voltage-current converting circuit and a ground node;
a deadlock detecting circuit for detecting that the PLL circuit is in a deadlock state; and
a control section, connected to the deadlock detecting circuit, for outputting the reset signal when the deadlock state detected by the deadlock detecting circuit continues for a predetermined time or more, and outputting the initialization signal during start-up of the PLL circuit and following the outputting of the reset signal.
2. The PLL circuit of claim 1 , characterized by comprising:
a fractional-N frequency divider for generating the feedback clock signal from the output clock signal; and
a ΔΣ controller for supplying a fractional-N frequency division ratio to the fractional-N frequency divider.
3. The PLL circuit of claim 2 , characterized in that
the ΔΣ controller, when receiving the initialization signal, supplies a predetermined integer frequency-division ratio to the fractional-N frequency divider based on the initialization signal.