Array substrate for a liquid crystal display device and method of manufacturing the same
View Patent ↗An array substrate for a liquid crystal display device includes a substrate, a gate line elongated in one direction, a data line crossing over the gate line, a thin film transistor near a crossing point of the gate and data lines and connected to the gate and data lines, an independent portion under the data line at the crossing point, the portion being separated from the gate line, and a pixel electrode connected to the thin film transistor. The independent portion may be inside the gate line. The parasitic capacitor between the gate line and the data line can be reduced and the amount of light from the backlight device can be reduced.
1. An array substrate for a liquid crystal display device, comprising:
a substrate;
a gate line elongated in one direction;
a data line crossing over the gate line;
a thin film transistor near a crossing point of the gate and data lines and connected to the gate and data lines;
an independent portion under the data line at the crossing point, the independent portion being separate from the gate line; and
a pixel electrode connected to the thin film transistor,
wherein the gate line has an open portion at the crossing point, and
wherein the independent portion is inside the open portion.
2. The array substrate according to claim 1 , wherein the independent portion is inside the gate line.
3. The array substrate according to claim 1 , wherein the independent portion is electrically floated and shields incident light to the thin film transistor.
4. The array substrate according to claim 1 , wherein the independent portion has the same material and the same layer as the gate line.
5. The array substrate according to claim 1 , further comprising a metal layer connected to the pixel electrode, wherein the metal layer overlaps the gate line to form a storage capacitor.
6. The array substrate according to claim 1 , wherein the thin film transistor includes a gate electrode connected to the gate line, an active layer of intrinsic amorphous silicon, and source and drain electrodes, wherein the source electrode is connected to the data line and the drain electrode is connected to the pixel electrode.
7. The array substrate according to claim 1 , wherein the pixel electrode includes one of indium-tin-oxide (ITO) and indium-zinc-oxide (IZO).
8. The array substrate according to claim 1 , wherein a first width of a portion of the gate line at the crossing portion is smaller than a second width of the other portion of the gate line.