Method and system for determining a clock input mode

1. A method, comprising:

receiving a first input signal from a first of two terminals designated as clock input terminals;

receiving a second input signal;

determining whether the first input signal and the second input signal satisfy a pre-determined condition, wherein the pre-determined condition includes a first condition and a second condition relating to the duration during which the first condition is met; and

selecting a clock input mode, based on whether the pre-determined condition is met, that indicates whether the clock input terminals provide a differential clock input or a second of the two clock input terminals provides a single-ended digital clock input.

2. The method of claim 1 , wherein the first condition is that the voltage of the first input signal is below the voltage of the second input signal.

3. The method of claim 1 , wherein the first condition is that the voltage of the first input signal is above the voltage of the second input signal.

4. The method of claim 1 , wherein the first condition is that the voltage of the first input signal is substantially equal to the voltage of the second input signal.

5. The method of claim 1 , wherein the step of selecting comprises:

generating a first clock mode enabling signal selecting a first clock input mode when the pre-determined condition is met;

generating a second clock mode enabling signal selecting a second clock input mode when the pre-determined condition is not met.

6. A method, comprising:

receiving a first input signal from a first of two terminals designated as clock input terminals;

receiving a second input signal;

determining whether the first input signal and the second input signal satisfy a pre-determined condition, wherein the pre-determined condition includes a first condition;

selecting a clock input mode, based on whether the pre-determined condition is met, that indicates whether the clock input terminals provide a differential clock input or a second of the two clock input terminals provides a single-ended digital clock input, wherein the step of selecting comprises:

generating a first clock mode enabling signal selecting a first clock input mode when the pre-determined condition is met; and

generating a second clock mode enabling signal selecting a second clock input mode when the pre-determined condition is not met;

wherein

the first clock input mode is a single-ended clock input mode; and

the second clock input mode is a differential clock input mode.

7. A clock mode selector, comprising:

a condition satisfaction detector having a first input signal from a first of two clock input terminals and a second input signal and capable of determining whether the first input signal and the second input signal satisfy a pre-determined condition, wherein the condition satisfaction detector comprises a first condition detector capable of detecting satisfaction of a first condition, wherein the condition satisfaction detector further comprises a second condition detector capable of detecting the length of duration during which the first condition is met; and

a clock mode determiner coupled to the output of the condition satisfaction detector and capable of producing a clock mode selection signal indicating whether the clock input terminals provide a differential clock input or a second of the two clock input terminals provides a single-ended digital clock input.

8. The apparatus of claim 7 , wherein the first condition is that the voltage of the first input signal is below the voltage of the second input signal.

9. The apparatus of claim 7 , wherein the first condition is that the voltage of the first input signal is above the voltage of the second input signal.

10. The apparatus of claim 7 , wherein the first condition is that the voltage of the first input signal is substantially equal to the voltage of the second input signal.

11. The apparatus of claim 7 , wherein the clock mode determiner:

outputs a signal indicating a first clock input mode when the pre-determined condition is met;

outputs a signal indicating a second clock input mode when the pre-determined condition is not met.

12. A clock mode selector, comprising:

a condition satisfaction detector having a first input signal from a first of two clock input terminals and a second input signal and capable of determining whether the first input signal and the second input signal satisfy a pre-determined condition;

a clock mode determiner coupled to the output of the condition satisfaction detector and capable of producing a clock mode selection signal indicating whether the clock input terminals provide a differential clock input or a second of the two clock input terminals provides a single-ended digital clock input, wherein the clock mode determiner

outputs a signal indicating a first clock input mode when the pre-determined condition is met;

outputs a signal indicating a second clock input mode when the pre-determined condition is not met;

wherein the first clock input mode is a single-ended clock mode and the second clock input mode is a differential clock mode.