HBT and field effect transistor integration
View Patent ↗Methods and systems for fabricating an integrated BiFET using two separate growth procedures are disclosed. Performance of the method fabricates the FET portion of the BIFET in a first fabrication environment. Performance of the method fabricates the HBT portion of the BiFET in a second fabrication environment. By separating the fabrication of the FET portion and the HBT portion in two or more separate reactors, the optimum device performance can be achieved for both devices.
1. A method of fabricating a BiFET device, the method comprising the steps of:
loading a substrate into a first fabrication environment;
forming a FET portion of the BiFET device on the substrate in the first fabrication environment;
removing the substrate from the first fabrication environment after formation of the FET portion of the BiFET device;
loading the substrate in a second fabrication environment; and
forming a HBT portion of the BiFET device on the substrate in the second fabrication environment, wherein the temperature is lowered to between 30° C. and 100° C. during the forming of the HBT portion of the BiFET device.
2. A method according to claim 1 wherein the FET portion of the BiFET device is substantially free of contamination from impurities introduced during formation of the HBT portion of the BiFET device.
3. A method according to claim 1 wherein the FET device is an HFET.
4. A method according to claim 3 wherein the HFET is a pHEMT.
5. A method according to claim 1 wherein the first fabrication environment is one of a molecular beam epitaxy or a metal-organic chemical vapor deposition reactor.
6. A method according to claim 1 wherein the second fabrication environment is one of a molecular beam epitaxy or a metal-organic chemical vapor deposition reactor.
7. A method according to claim 1 wherein the first fabrication environment and the second fabrication environment are of different types.
8. A method according to claim 1 wherein the substrate is one of a GaAs or InP substrate.
9. A method according to claim 1 wherein the temperature is lowered during the formation of a collector region of the HBT portion of the BiFET device.
10. A method according to claim 1 wherein the temperature is lowered during the formation of a collector region of the HBT portion of the BiFET device.
11. A method according to claim 1 wherein the temperature during an oxide desorb process is lowered by at least 50° C. prior to the growth of a subcollector region.
12. A BiFET device fabricated according the method of claim 1 .
13. A method of fabricating a BiFET device, the method comprising the steps of:
loading a substrate into a first fabrication environment;
forming a FET portion of the BiFET device on the substrate in the first fabrication environment;
removing the substrate from the first fabrication environment after formation of the FET portion of the BiFET device;
loading the substrate in a second fabrication environment; and
forming a HBT portion of the BiFET device on the substrate in the second fabrication environment,
wherein the temperature is lowered during the forming of the HBT portion of the BiFET device, and
wherein the temperature during an oxide desorb process is lowered by at least 50° C. prior to the growth of a subcollector region.
14. A method according to claim 13 wherein the FET portion of the BiFET device is substantially free of contamination from impurities introduced during formation of the HBT portion of the BiFET device.
15. A method according to claim 13 wherein the FET device is an HFET.
16. A method according to claim 15 wherein the HFET is a pHEMT.
17. A method according to claim 13 wherein the first fabrication environment is one of a molecular beam epitaxy or a metal-organic chemical vapor deposition reactor.
18. A method according to claim 13 wherein the second fabrication environment is one of a molecular beam epitaxy or a metal-organic chemical vapor deposition reactor.
19. A method according to claim 13 wherein the first fabrication environment and the second fabrication environment are of different types.
20. A method according to claim 13 wherein the substrate is one of a GaAs or InP substrate.
21. A method according to claim 13 wherein the temperature is lowered during the formation of a collector region of the HBT portion of the BiFET device.
22. A method according to claim 13 wherein the temperature is lowered to between 30° C. and 100° C.
23. A method according to claim 22 wherein the temperature is lowered during the formation of a collector region of the HBT portion of the BiFET device.
24. A BiFET device fabricated according the method of claim 13 .