Isolated junction field-effect transistor
View Patent ↗Various integrated circuit devices, in particular a junction field-effect transistor (JFET), are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described.
1. An isolated junction field-effect transistor (JFET) formed in a semiconductor substrate of a first conductivity type, the substrate not comprising an epitaxial layer, the isolated JFET comprising:
a floor isolation/bottom gate region of a second conductivity type opposite to the first conductivity type submerged in the substrate;
a trench extending from a surface of the substrate into the floor isolation/bottom gate region, the trench comprising a central portion filled with a conductive material and having a dielectric material lining the walls of the trench, a bottom of the trench being embedded in the floor isolation/bottom gate region, the conductive material being in contact with the floor isolation/bottom gate region, the trench and the floor isolation region together forming an isolated pocket of the substrate;
a source region at the surface of the substrate in the isolated pocket;
a drain region spaced apart from the source region at the surface of the substrate in the isolated pocket;
a top gate region at the surface of the substrate between the source region and the drain region; and
a channel region extending between the source region and the drain region and located below the top gate region and above the floor isolation/bottom gate region.
2. The isolated JFET of claim 1 comprising a first dielectric-filled trench located horizontally between the source region and the top gate region and a second dielectric-filled trench located horizontally between the drain region and the top gate region.
3. The isolated JFET of claim 1 wherein the source, drain, and channel regions are of the first conductivity type, and the top gate is of the second conductivity type.
4. The isolated JFET of claim 1 wherein a lower boundary of the floor isolation/bottom gate region forms a PN junction with the substrate.