Isolated quasi-vertical DMOS transistor
Various integrated circuit devices, in particular a quasi-vertical DMOS transistor, are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described.
1 . An isolated quasi-vertical DMOS (QVDMOS) transistor formed in a semiconductor substrate of a first conductivity type, the substrate not comprising an epitaxial layer, the isolated QVDMOS transistor comprising:
a floor isolation region of a second conductivity type opposite to the first conductivity type submerged in the substrate;
a trench extending from a surface of the substrate at least to the floor isolation region, the trench having a central conductive portion and a dielectric material lining the walls of the trench, the trench and the floor isolation region together forming an isolated pocket of the substrate;
a source region of the second conductivity type at the surface of the substrate in the isolated pocket;
a gate located atop a gate dielectric layer above an area of the surface of the substrate adjacent the source region;
a body region of the first conductivity type in the isolated pocket, the body region extending under the gate; and
a drift region of the second conductivity type in the isolated pocket extending between the floor isolation region and the body region.
2 . The isolated QVDMOS transistor of claim 1 wherein a drain of the QVSMOS transistor comprises the floor isolation region.
3 . The isolated QVDMOS transistor of claim 1 wherein the central conductive portion provides contact from the floor isolation region to the surface of the substrate.