Method of growing gan crystal on silicon substrate, and light emitting device and method of manufacturing thereof
View Patent ↗Example embodiments are directed to a method of growing GaN single crystals on a silicon substrate, a method of manufacturing a GaN-based light emitting device using the silicon substrate, and a GaN-based light emitting device. The method of growing the GaN single crystals may include forming a buffer layer including a TiN group material or other like material on a silicon substrate, forming a nano-pattern including silicon oxide on the buffer layer, and growing GaN single crystals on the buffer layer and the nano-pattern.
1. A method of manufacturing a light emitting device, comprising:
growing GaN single crystals by forming a buffer layer including a TiN group material contacting a silicon substrate, forming a nano-pattern including silicon oxide on the buffer layer, and growing the GaN single crystals on the buffer layer and the nano-pattern;
forming an n-GaN layer on the buffer layer and the nano-pattern;
forming an active layer on the n-GaN layer;
forming a p-GaN layer on the active layer; and
forming a p-electrode and an n-electrode, one of the p-electrode and the n-electrode being disposed on a surface of the silicon substrate,
wherein forming the nano-pattern includes forming a silicon oxide layer by depositing SiO 2 on the buffer layer, forming a plurality of metal nano-dots on the silicon oxide layer, and dry etching the silicon oxide layer using the metal nano-dots as a mask.
2. The method of claim 1 , wherein the metal nano-dots are formed by anodizing an aluminum thin film after depositing the aluminum thin film on the silicon oxide layer.
3. The method of claim 1 , wherein the metal nano-dots are formed by annealing an Au thin film after depositing the Au thin film on the silicon oxide layer.
4. The method of claim 1 , wherein the buffer layer is formed of Al x Ti 1-x N, where 0≦x≦0.5, or Cr x Ti 1-x N, where 0≦x≦0.5.
5. The method of claim 4 , wherein the thickness of the buffer layer is in a range of 1 to 50 nm.
6. The method of claim 1 , wherein the p-electrode is formed on the p-GaN layer, and the n-electrode is formed on a lower surface of the silicon substrate.
7. The method of claim 1 , wherein the p-electrode is formed on the p-GaN layer, and the n-electrode is formed on exposed portions of the n-GaN layer formed by etching portions of the active layer and the p-GaN layer.