Method for fabricating semiconductor memory

1. A method for fabricating a semiconductor memory having a semiconductor substrate having a concave portion and a convex portion, an element isolation region, a gate electrode and a charge storing layer, the method comprising:

(a) forming the element isolation region in the concave portion of the semiconductor substrate;

(b) forming a layer made of a gate electrode material so as to cover the concave portion of the semiconductor substrate and the element isolation region;

(c) forming the gate electrode by forming a mask on a surface of the layer made of a gate electrode material so that a height from an upper surface of the convex portion to the surface of the mask is higher than a height from the surface of the element isolation region to the upper surface of the convex portion and by patterning the layer made of the gate electrode material;

(d) forming the charge storing layer at on least one of side surfaces of the gate electrode in contact with the convex portion of the semiconductor substrate; and

(e) forming a sidewall on at least a part of the charge storing layer.

2. The method for fabricating a semiconductor memory according to claim 1 , wherein the layer made of the gate electrode material is formed so that a height from the upper surface of the convex portion to the upper surface of the layer made of the gate electrode material is higher than a height from the surface of the element isolation region to the upper surface of the convex portion.

3. The method for fabricating a semiconductor memory according to claim 1 , wherein the convex portion includes a channel forming region, an extension forming region provided so as to sandwich the channel forming region, and source/drain forming regions provided so as to sandwich the channel forming region and the extension forming region;

the forming of the gate electrode (c) includes forming the gate electrode on the channel forming region; and

the forming of the sidewall (e) includes

(e1) forming a sidewall material on the semiconductor substrate on which the charge storing layer is formed, and

(e2) exposing the source/drain regions by anisotropic etching the sidewall material and the charge storing layer.

4. The method for fabricating a semiconductor memory according to claim 2 , wherein the convex portion includes a channel forming region, an extension forming region provided so as to sandwich the channel forming region, and source/drain forming regions provided so as to sandwich the channel forming region and the extension forming region;

the forming of the gate electrode (c) includes forming the gate electrode on the channel forming region; and

the forming of the sidewall (e) includes

(e1) forming a sidewall material on the semiconductor substrate on which the charge storing layer is formed, and

(e2) exposing the source/drain regions by anisotropic etching the sidewall material and the charge storing layer.

5. The method for fabricating a semiconductor memory according to claim 3 , further comprising:

(f) forming an extension region in the extension forming region after the forming of the gate electrode (c) and before the forming of the charge storing layer (d); and

(g) forming source/drain regions after the forming of the sidewall (e).

6. The method for fabricating a semiconductor memory according to claim 4 , further comprising:

(f) forming an extension region in the extension forming region after the forming of the gate electrode (c) and before the forming of the charge storing layer (d); and

(g) forming source/drain regions after the forming sidewall (e).