Image processing circuit
an image processing circuit includes a memory storing an image data, which includes a plurality of line data disposed regularly a first module performing a plurality of thinning processes, at each of which a plurality of line data are readout from the memory, and at each of which one line data is processed by using the readout line data, wherein the processed line data is restored in the memory, and wherein the first image processing module outputs a first signal after the thinning processes for a certain times are completed, and a second module, which start its operation in response to the first completion signal, performing a similar image-process performed by the first module, wherein the second image processing module outputs a second completion signal after the thinning processes for the entire image data stored in the memory are completed.
1 . An image processing circuit, comprising:
a memory storing an image data, which includes a plurality of line data disposed regularly;
a first image processing module including a first arithmetic unit and a counter, the first arithmetic unit performing an image-process, which includes a plurality of thinning processes, at each of which a plurality of line data are readout from the memory, and at each of which one line data is processed by using the line data readout by the first image processing module, and the counter counting a number of times that the thinning processes are performed, wherein the processed line data is restored in the memory, and wherein the first image processing module outputs a first completion signal after the thinning processes for a certain times are completed; and
a second image processing module, which start its operation in response to the first completion signal, including a second arithmetic unit and a judgment unit, the second arithmetic unit performing an image-process, which includes a plurality of thinning processes, at each of which a plurality of line data, which are partially or totally processed by the first image processing module, are readout from the memory, and at each of which one line data is processed by using the line data readout by the second image processing module, wherein the processed line data is restored in the memory, and wherein the second image processing module outputs a second completion signal after the thinning processes for the entire image data stored in the memory are completed, and outputs the judgment signals indicating that a predetermined image-process under which a predetermined requirement is satisfied is completed, based on a judgment result made by the judgment unit.
2 . An image processing circuit as claimed in claim 1 , wherein the memory is a two-port memory, whereby the first and the second image processing modules independently and concurrently access the two-port memory.
3 . An image processing circuit as claimed in claim 1 , wherein the readout line data is three lines of the line data, which are disposed sequentially, and the thinning process is performed to the middle of the line data.
4 . An image processing circuit, comprising:
a memory storing an image data, which includes a plurality of line data disposed regularly;
a first image processing module including a first arithmetic unit and a counter, the first arithmetic unit performing an image-process, which includes a plurality of thinning processes, at each of which a plurality of line data are readout from the memory, and at each of which one line data is processed by using the line data readout by the first image processing module, and the counter counting a number of times that the thinning processes are performed, wherein the processed line data is restored in the memory, and wherein the first image processing module outputs a first completion signal whenever the thinning process is completed,
a second image processing module, which start its operation in response to the first completion signal, including a second arithmetic unit and a judgment unit, the second arithmetic unit performing an image-process, which includes a plurality of thinning processes, at each of which a plurality of line data, which are partially or totally processed by the first image processing module, are readout from the memory, and at each of which one line data is processed by using the line data readout by the second image processing module, wherein the processed line data is restored in the memory, and wherein the second image processing module outputs a second completion signal after the thinning processes for an entire image data stored in the memory are completed, and outputs the judgment signals indicating that a predetermined image-process under which a predetermined requirement is satisfied is completed, based on a judgment result made by the judgment unit.
5 . An image processing circuit as claimed in claim 4 , wherein the memory is a two-port memory, whereby the first and the second image processing modules independently and concurrently access the two-port memory.
6 . An image processing circuit as claimed in claim 4 , wherein the readout line data is three lines of the line data, which are disposed sequentially, and the thinning process is performed to the middle of the line data.
7 . An image processing circuit, comprising:
a memory storing an image data, which includes a plurality of line data disposed regularly;
a first image processing module including a first arithmetic unit, a counter and the first judgment unit, the first arithmetic unit performing an image-process, which includes a plurality of thinning processes, at each of which a plurality of line data are readout from the memory, and at each of which one line data is processed by using the line data readout by the first image processing module, the counter counting a number of times that the thinning processes are performed, wherein the processed line data is restored in the memory, and the first judgment unit judging whether or not a predetermined image-process under which a predetermined requirement is satisfied is completed after the thinning processes are performed to the entire image data stored in the memory, and wherein the first image processing module outputs a first completion signal after the thinning processes for a certain times are completed; and
a second image processing module, which start its operation in response to the first completion signal, including a second arithmetic unit and a second judgment unit, the second arithmetic unit performing an image-process, which includes a plurality of thinning processes, at each of which a plurality of line data, which are partially or totally processed by the first image processing module, are readout from the memory, and at each of which one line data is processed by using the line data readout by the second image processing module, wherein the processed line data is restored in the memory, wherein the second image processing module outputs a second completion signal after the thinning processes for an entire image data stored in the memory are completed, and outputs the judgment signals indicating that a predetermined image-process under which the predetermined requirements are satisfied is completed, based on a judgment result made by the second judgment unit, and wherein the second image processing module outputs a request signal for obtaining an allowance to access the memory, and accesses the memory in response to an allowance signal outputted from the first image processing module at the time that the first image processing module does not access the memory.
8 . An image processing circuit as claimed in claim 7 , wherein the memory is a single-port memory.
9 . An image processing circuit as claimed in claim 7 , wherein the readout line data is three lines of the line data, which are disposed sequentially, and the thinning process is performed to the middle of the line data.