A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6 , and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3 . Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.
1. A data processor comprising:
a first processing unit providing a plurality of address signals and receiving instructions;
a second processing unit;
a first address bus coupled to said first processing unit for providing said address signals;
a first data bus coupled to said first processing unit for receiving said instructions; and
a first memory coupled to said first address bus and said first data bus,
wherein said instructions include first instructions of said first processing unit and second instructions of said second processing unit, and
wherein said first processing unit receives said second instructions via said first data bus in response to said address signals provided by said first address bus, and said first processing unit provides a result of decoding said second instructions to said second processing unit.
2. A data processor according to claim 1 ,
wherein said first processing unit includes a decoder for decoding said first instructions and said second instructions from said first memory via said first data bus.
3. A data processor according to claim 2 ,
wherein said first processing unit includes an instruction register which stores said first and second instructions from said first memory.
4. A data processor according to claim 3 ,
wherein said instruction register is operable to store a plurality of said first and second instructions.
5. A data processor according to claim 1 , further including:
a second address bus coupled to said first processing unit for providing said address signals;
a second data bus coupled to said second processing unit; and
a second memory coupled to said second address bus and said second data bus,
wherein said second processing unit receives data signals from said second memory in response to said address signals from said first processing unit.
6. A data processor formed on a single semiconductor device, comprising:
a first processing unit generating a plurality of address signals and receiving a plurality of instructions;
a second processing unit;
a first bus coupled to said first processing unit;
a second bus coupled to said first processing unit and said second processing unit; and
a first memory coupled to said first bus,
wherein said first processing unit provides said address signals to said first bus, and said first processing unit receives and decodes said instructions from said first bus in response to said address signals,
wherein said plurality of instructions includes a first instruction for said first processing unit and a second instruction for said second processing unit, and
wherein said first processing unit decodes said second instruction, and provides a decoding result of said second instruction to said second processing unit.
7. A data processor according to claim 6 ,
wherein said first processing unit decodes said first instruction, and said first processing unit executes said first instruction.
8. A data processor according to claim 7 ,
wherein said first memory is operable to store said first instructions and said second instructions.
9. A data processor according to claim 6 ,
wherein said second processing unit receives data signals via said second bus in response to said address signals from said first processing unit.