Vertically mountable semiconductor device package
View Patent ↗A semiconductor package that includes a die with electrodes on opposite surfaces thereof and respective conductive clip electrically and mechanically coupled to the electrode and configured for vertical mounting of the package.
1. A semiconductor package, comprising:
a power MOSFET having a drain electrode on one surface thereof and a source electrode on another opposite surface thereof;
a first metallic clip that includes a first web portion having a surface electrically and mechanically coupled to said drain electrode by a conductive adhesive, and a first plurality of external connection terminal leads extending from an edge of and substantially coplanar to said first web portion along a direction away from a peripheral wall of said power MOSFET;
said first metallic clip further including a wall that extends from said first web portion and is spaced from and disposed opposite said peripheral wall of said power MOSFET; and
a second metallic clip that includes a second web portion having a surface electrically and mechanically coupled to said source electrode by a conductive adhesive, and at least a second external connection terminal lead extending from an edge of said second web portion along said direction away from said peripheral wall of said power MOSFET.
2. The semiconductor package of claim 1 , further comprising a gate electrode on said another opposite surface of said power MOSFET and a third metallic clip that includes a third web portion having a surface electrically and mechanically coupled to said gate electrode by a conductive adhesive, and at least one third external connection terminal lead extending from an edge of said third web portion along said direction away from said peripheral wall of said power MOSFET.
3. The semiconductor package of claim 2 , further comprising a thermally conductive dielectric insert thermally coupled to said second and third metallic clips.
4. The semiconductor package of claim 3 , wherein said thermally conductive dielectric insert comprises a ceramic.
5. The semiconductor package of claim 3 , wherein said thermally conductive dielectric insert comprises glass.
6. The semiconductor package of claim 3 , further comprising a filler body sealing said power MOSFET.
7. The semiconductor package of claim 3 , wherein said thermally conductive dielectric insert is mechanically coupled to said first metallic clip.
8. The semiconductor package of claim 2 , wherein each said external connection terminal lead includes a respective connection surface readied for connection to an external pad of a circuit board using a conductive adhesive.
9. The semiconductor package of claim 2 , wherein each said external connection terminal lead is configured for insertion in a respective receptacle on a circuit board.
10. The semiconductor package of claim 1 , wherein each said first plurality of external connection terminal leads and said second external connection terminal lead includes a respective connection surface readied for connection to a conductive pad of a circuit board using a conductive adhesive.
11. The semiconductor package of claim 1 , wherein each said first plurality of external connection terminal leads and said second external connection terminal lead is configured for insertion in a respective receptacle of a circuit board.
12. A semiconductor package, comprising:
a power MOSFET having a drain electrode on one surface thereof and a source electrode on another opposite surface thereof;
a first metallic clip that includes a first web portion having a surface electrically and mechanically coupled to said drain electrode by a conductive adhesive, and a first plurality of external connection terminal leads extending .from an edge of and substantially coplanar to said first web portion along a direction away from a peripheral wall of said power MOSFET;
said first metallic clip further including a wall that extends from said first web portion and is spaced from and disposed opposite said peripheral wall of said power MOSFET; and
a second metallic clip that includes a second web portion having a surface electrically and mechanically coupled to said source electrode by a conductive adhesive, and at least a second external connection terminal lead extending from an edge of a bent portion of said second web portion along said direction away from said peripheral wall of said power MOSFET, wherein said bent portion of said second web portion provides a gap wider than the thickness of said power MOSFET between said second external connection terminal lead and said first plurality of external connection terminal leads.
13. The semiconductor package of claim 12 , further comprising a gate electrode on said another opposite surface of said power MOSFET and a third metallic clip that includes a third web portion having a surface electrically and mechanically coupled to said gate electrode by a conductive adhesive, and at least one third external connection terminal lead extending from an edge of a bent portion of said third web portion along said direction away from said peripheral wall of said power MOSFET, wherein said bent portion provides a gap wider than the thickness of said power MOSFET between said third external connection terminal lead and said first plurality of external connection terminal leads.
14. The semiconductor package of claim 13 , further comprising a thermally conductive dielectric insert thermally coupled to said second and third metallic clips.
15. The semiconductor package of claim 12 , wherein each said external connection terminal lead includes a respective connection surface readied for connection to an external pad of a circuit board using a conductive adhesive.