Semiconductor device with bipolar transistor
View Patent ↗A semiconductor device includes a semiconductor layer formed on an insulation layer and having an MOS (Metal Oxide Semiconductor) transistor area and a bi-polar transistor area; an MOS transistor formed in the MOS transistor area; and a bi-polar transistor formed in the bi-polar transistor area. The MOS transistor includes a source area of a second conductive type; a drain area of the second conductive type; and a channel area of a first conductive type. The MOS transistor further includes a gate electrode formed on the channel area with a first oxide layer inbetween. The bi-polar transistor includes a collector area of the second conductive type; an emitter area of the second conductive type; and a base area of the first conductive type. The bi-polar transistor further includes a dummy pattern formed on the base area with a second oxide layer inbetween.
1. A semiconductor device comprising:
a semiconductor layer formed on an insulation layer, said semiconductor layer having an MOS (Metal Oxide Semiconductor) transistor area and a bi-polar transistor area;
an MOS transistor formed in the semiconductor layer in the MOS transistor area, said MOS transistor including a source area of a second conductive type; a drain area of the second conductive type; and a channel area of a first conductive type formed between the source area and the drain area, said MOS transistor further including a gate electrode formed on the channel area with a first oxide layer inbetween; and
a bi-polar transistor formed in the semiconductor layer in the bi-polar transistor area, said bi-polar transistor including a collector area of the second conductive type; an emitter area of the second conductive type; a base area of the first conductive type formed between the collector area and the emitter area; a base contact area of the first conductive type adjacent to the base area in a channel width direction; and a dummy pattern formed on the base area with a second oxide layer inbetween, said base area being formed in a rectangular shape having two long sides along the channel width direction and two short sides perpendicular to the long sides;
a first LDD (Lightly Doped Drain) area of the first conductive type formed in the base area near a boundary between the base area and the base contact area along at least one of the short sides, said first LDD area having an impurity concentration lower than that of the base contact area;
a second LDD (Lightly Doped Drain) area of the second conductive type formed in the base area near a boundary along one of the long sides between the base area and the collector area and a boundary along the other of the long sides between the base area and the emitter area, said second LDD area having an impurity concentration lower than that of the collector area and the emitter area;
a third LDD (Lightly Doped Drain) area of the second conductive type formed in the channel area near a boundary between the channel area and the source area and a boundary between the channel area and the drain area, said third LDD (Lightly Doped Drain) area having an impurity concentration lower than that of the source area and the drain area; and
a fourth LDD (Lightly Doped Drain) area of the second conductive type near a boundary between the channel area and the source area and a boundary between the channel area and the drain area, said fourth LDD (Lightly Doped Drain) area haying an impurity concentration lower than that of the source area and the drain area.
2. The semiconductor device according to claim 1 , wherein said gate electrode is formed of a first material, said dummy pattern being formed of a second material the same as the first material.
3. The semiconductor device according to claim 1 , wherein said dummy pattern has an impurity concentration less than 1×10 19 cm −3 .
4. The semiconductor device according to claim 1 , wherein said dummy pattern is electrically connected to a ground wiring.