IP Library Granted Patent US 8,003,307
Granted Patent B2
US 8,003,307 · App. 12/076,334 · Granted Aug 23, 2011

Photo mask and method for fabricating image sensor using the same

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,003,307
App. No.
12/076,334
Granted
Aug 23, 2011
Kind
B2
Abstract

A method for fabricating an image sensor includes forming an insulation layer over a substrate in a logic circuit region and a pixel region, forming a photoresist over the insulation layer, patterning the photoresist to form a photoresist pattern where the insulation layer in the pixel region is exposed and the insulation layer in the logic circuit region is not exposed, wherein a thickness of the photoresist pattern is gradually decreased in an interfacial region between the pixel region and the logic circuit region in a direction of the logic circuit region to the pixel region, and performing an etch back process over the insulation layer and the photoresist pattern in conditions that an etch rate of the photoresist pattern are substantially the same as that of the insulation layer.

Claims (29)

1. A method, comprising:

forming an insulation layer over a substrate in both a logic circuit region and a pixel region of an image sensor;

forming a photoresist over the insulation layer;

patterning the photoresist to form a photoresist pattern that exposes the insulation layer in the pixel region but not in the logic circuit region, wherein said patterning includes gradually decreasing a thickness of the photoresist pattern in an interfacial region between the pixel region and the logic circuit region in a direction from the logic circuit region to the pixel region; and

performing an etch back process over the insulation layer and the photoresist pattern in conditions that result in an etch rate of the photoresist pattern being substantially the same as an etch rate of the insulation layer.

2. The method of claim 1 , further comprising forming an anti-reflection layer over the insulation layer prior to said forming a photoresist.

3. The method of claim 2 , wherein said performing an etch back process results in the photoresist pattern in the interfacial region having an angle of slope that ranges from approximately 0.4 degrees to approximately 15 degrees.

4. The method of claim 2 , further comprising forming a color filter over the insulation layer in the pixel region after said performing an etch back process.

5. The method of claim 1 , wherein said performing an etch back process results in the photoresist pattern in the interfacial region having an angle of slope that ranges from approximately 0.4 degrees to approximately 15 degrees.

6. The method of claim 1 , wherein said forming an insulation layer comprises using an oxide to form the insulation layer.

7. The method of claim 6 , wherein said performing an etch back process comprises:

using a pressure of approximately 50 mT to approximately 1,500 mT;

using a power of approximately 300 W to approximately 1,000 W; and

using CHF 3 gas at a flow rate of approximately 10 sccm to approximately 50 sccm, O 2 gas at a flow rate of approximately 10 sccm to approximately 50 sccm, and Ar gas at a flow rate of approximately 300 sccm to approximately 1,500 sccm.

8. The method of claim 1 , wherein said forming an insulation layer comprises forming the insulation layer to a thickness that ranges from approximately 40,000 Å to approximately 70,000 Å.

9. The method of claim 8 , wherein said forming an insulation layer comprises forming the insulation layer to a thickness of approximately 46,000 Å.

10. The method of claim 9 , wherein said performing an etch back process comprises removing approximately 15,000 Å in thickness of the insulation layer.

11. The method of claim 1 , further comprising forming a color filter over the insulation layer in the pixel region after said performing an etch back process.

12. A method, comprising:

forming an insulation layer over a substrate in both a logic circuit region and a pixel region of an image sensor;

forming a photoresist over the insulation layer;

preparing a photo mask having a pattern by which an amount of light transferred onto the substrate is gradually decreased in a direction from the logic circuit region to the pixel region, wherein the pattern of the photo mask corresponds to an interfacial region between the pixel region and the logic circuit region;

patterning the photoresist by using the photo mask to form a photoresist pattern that exposes the insulation layer in the pixel region but not in the logic circuit region, wherein said patterning the photoresist includes gradually decreasing a thickness of the photoresist pattern in the interfacial region in a direction from the logic circuit region to the pixel region; and

performing an etch back process on the exposed insulation layer.

13. The method of claim 12 , further comprising forming an anti-reflection layer over the insulation layer prior to said forming a photoresist.

14. The method of claim 13 , wherein said forming a photoresist comprises forming a positive photoresist.

15. The method of claim 13 , further comprising forming a color filter over the insulation layer in the pixel region after said performing an etch back process.

16. The method of claim 12 , wherein said forming a photoresist comprises forming a positive photoresist.

17. The method of claim 12 , further comprising forming a color filter over the insulation layer in the pixel region after said performing an etch back process.

Assignments (5)
MERGER Recorded Jul 22, 2011
From: CROSSTEK CAPITAL, LLC
To: INTELLECTUAL VENTURES II LLC
Reel/Frame 026637/0632 →
PARTIAL RELEASE OF SECURITY INTEREST Recorded Aug 10, 2009
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 023075/0054 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2009
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: CROSSTEK CAPITAL, LLC
Reel/Frame 022764/0270 →
AFTER-ACQUIRED INTELLECTUAL PROPERTY KUN-PLEDGE AGREEMENT Recorded Feb 18, 2009
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE
Reel/Frame 022277/0133 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 17, 2008
From: NAM, HYUN-HEE; PARK, JEONG-LYEOL
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 020709/0117 →