Semiconductor device having a resistor and methods of forming the same
In a semiconductor device and a method of making the same, the semiconductor device comprises a substrate including a first region and a second region. At least one first gate structure is on the substrate in the first region, the at least one first gate structure including a first gate insulating layer and a first gate electrode layer on the first gate insulating layer. At least one isolating structure is in the substrate in the second region, a top surface of the isolating structure being lower in height than a top surface of the substrate. At least one resistor pattern is on the at least one isolating structure.
1. A semiconductor device comprising:
a substrate including a first region and a second region;
at least one first gate structure on the substrate in the first region, the at least one first gate structure including a first gate insulating layer and a first gate electrode layer on the first gate insulating layer;
at least one isolating layer in the substrate in the second region; and
at least one resistor pattern on the at least one isolating layer,
wherein a top surface of the isolating layer at a side of the at least one resistor pattern is lower in height than a top surface of the substrate.
2. The semiconductor device of claim 1 wherein the first region comprises a cell region of the device, wherein the at least one first gate structure comprises at least one cell gate structure, and wherein the second region comprises a peripheral region of the device.
3. The semiconductor device of claim 1 :
wherein the first gate insulating layer comprises a tunnel insulating layer; and
wherein the at least one first gate structure comprises the tunnel insulating layer, a charge storage layer on the tunnel insulating layer, a blocking insulating layer on the charge storage layer and a first gate electrode layer on the blocking insulating layer.
4. The semiconductor device of claim 3 wherein the at least one first gate structure comprises multiple first gate structures and wherein in a subset of the multiple first gate structures, the first gate electrode layer and the charge storage layer are in direct electrical contact.
5. The semiconductor device of claim 1 wherein the at least one first gate structure includes a silicide region at a top portion thereof.
6. The semiconductor device of claim 5 wherein no silicide region is present on the at least one resistor pattern.
7. The semiconductor device of claim 1 wherein the at least one first gate structure includes a metal layer at a top portion thereof.
8. The semiconductor device of claim 7 wherein no metal layer is present on the at least one resistor pattern.
9. The semiconductor device of claim 1 wherein the at least one first gate structure forms a gate for a non-volatile memory cell in the first region.
10. The semiconductor device of claim 1 further comprising an insulating layer on the at least one isolating layer and below the resistor pattern.
11. A semiconductor device comprising:
a substrate including a first region and a second region;
at least one first gate structure on the substrate in the first region, the at least one first gate structure including a first gate insulating layer and a first gate electrode layer on the first gate insulating layer;
at least one isolating layer in the substrate in the second region; and
at least one resistor pattern on the at least one isolating layer,
wherein a topmost surface of the isolating layer is lower in height than a top surface of the substrate.