Phase locked loop
View Patent ↗A disclosed exemplary embodiment is a phase locked loop comprising a main charge pump driven by a phase error signal, and providing a first input to a loop filter. An auxiliary charge pump driven by the phase error signal feeds a second input of the loop filter. The loop filter can be an active loop filter comprising an operational amplifier and a feedback RC network. The first input of the active loop filter can be an inverting input of the operational amplifier and the second input can be a non-inverting input of the operational amplifier. An on-chip stabilizing capacitor fed by the auxiliary charge pump and coupled to the second input of the loop filter is significantly smaller than the conventional stabilizing capacitors. The loop filter outputs a regulating voltage for regulating the oscillation frequency of a voltage controlled oscillator in the phase locked loop.
1. A phase locked loop comprising:
a main charge pump driven by a phase error signal and feeding a first input of a loop filter;
an auxiliary charge pump driven by said phase error signal and feeding a second input of said loop filter, said auxiliary charge pump being smaller than said main charge pump;
an on-chip stabilizing capacitor fed by said auxiliary charge pump and coupled to said second input of said loop filter;
said loop filter providing a regulating voltage for regulating a frequency of a voltage controlled oscillator in said phase locked loop.
2. The phase locked loop of claim 1 wherein said loop filter comprises an active loop filter.
3. The phase locked loop of claim 2 wherein said active loop filter comprises an operational amplifier.
4. The phase locked loop of claim 3 wherein said first input of said loop filter is an inverting input of said operational amplifier.
5. The phase locked loop of claim 3 wherein said second input of said loop filter is a non-inverting input of said operational amplifier.
6. The phase locked loop of claim 3 wherein a feedback RC network is coupled across an output and an inverting input of said operational amplifier.
7. The phase locked loop of claim 6 wherein said feedback RC network comprises one resistor and one capacitor.
8. The phase locked loop of claim 1 wherein an output of said voltage controlled oscillator is coupled to a divide by N.
9. The phase locked loop of claim 8 wherein an output of said divide by N and a reference clock are fed to a phase frequency detector.
10. The phase locked loop of claim 9 wherein said phase frequency detector generates said phase error signal by comparing a phase of said output of said divide by N with a phase of said reference clock.
11. The phase locked loop of claim 1 wherein said main charge pump and said auxiliary charge pump produce respective output voltages corresponding to said phase error signal.
12. A low phase noise PLL comprising:
a main charge pump driven by a phase error signal and feeding a first input of an active loop filter;
an auxiliary charge pump driven by said phase error signal and feeding a second input of said active loop filter, said auxiliary charge pump being smaller than said main charge pump;
an on-chip stabilizing capacitor fed by said auxiliary charge pump and coupled to said second input of said active loop filter;
said active loop filter providing a regulating voltage for regulating a frequency of a voltage controlled oscillator in said low phase noise PLL.
13. The low phase noise PLL of claim 12 wherein said active loop filter comprises an operational amplifier.
14. The low phase noise PLL of claim 13 wherein said first input of said active loop filter is an inverting input of said operational amplifier.
15. The low phase noise PLL of claim 13 wherein said second input of said active loop filter is a non-inverting input of said operational amplifier.
16. The low phase noise PLL of claim 13 wherein a feedback RC network is coupled across an output and an inverting input of said operational amplifier.
17. The low phase noise PLL of claim 16 , wherein said feedback RC network comprises one resistor and one capacitor.
18. The low phase noise PLL of claim 12 wherein an output of said voltage controlled oscillator is coupled to a divide by N.
19. The low phase noise PLL of claim 18 wherein an output of said divide by N and a reference clock are fed to a phase frequency detector.
20. The low phase noise PLL of claim 19 wherein said phase frequency detector generates said phase error signal by comparing a phase of said output of said divide by N with a phase of said reference clock.