IP Library Granted Patent US 8,400,442
Granted Patent B2
US 8,400,442 · App. 12/078,892 · Granted Mar 19, 2013

Display, method for driving display, electronic apparatus

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Quick Facts
Patent No.
US 8,400,442
App. No.
12/078,892
Granted
Mar 19, 2013
Kind
B2
Abstract

A display includes: a pixel array section configured to include power feed lines, scan lines disposed along rows, signal lines disposed along columns, and pixels that are disposed at intersections of the scan lines and the signal lines and are arranged in a matrix, each of the pixels including a drive transistor and a light-emitting device, one of a pair of current terminals as source and drain of the drive transistor being connected to the power feed line, and a power supply scanner configured to sequentially switch potential of each power feed line between higher potential and lower potential, wherein the power supply scanner switches the higher potential applied to the power feed line between first higher potential and second higher potential at different levels in a predetermined sequence.

Claims (14)

1. A display, comprising:

a pixel array section configured to include power feed lines, scan lines disposed along rows, signal lines disposed along columns, and pixels that are disposed at intersections of the scan lines and the signal lines and are arranged in a matrix, each of the pixels including a drive transistor and a light-emitting device, one of a pair of current terminals as source and drain of the drive transistor being connected to the power feed line; and

a power supply scanner configured to sequentially switch potential of each power feed line between a first higher potential, a second higher potential, and a lower potential, wherein

the power supply scanner switches the power feed line between first higher potential and second higher potential at different levels in a predetermined sequence,

the power supply scanner includes a shift register and output buffers that are each connected to a respective one of stages of the shift register,

the shift register sequentially produces a switch signal for each of the stages,

the output buffer is provided between a power supply line and a ground line, and the output buffer switches potential between the first or second higher potential on a power supply line side and the lower potential on a ground line side in accordance with the switch signal and applies the potential to a corresponding one of the power feed lines,

the first higher potential and the second higher potential are supplied to the power supply line side of the output buffer in such a manner as to be alternately switched to each other, and a first lower potential and a second lower potential lower than the first lower potential are supplied to the ground line side of the output buffer in such a manner as to be alternately switched to each other in linkage with the switching between the first higher potential and the second higher potential, and

the switching between the first lower potential and the second lower potential is so carried out that voltage applied between source and drain of a transistor included in the output buffer provided between the power supply line and the ground line is prevented from surpassing insulation breakdown voltage.

2. The display according to claim 1 , wherein

the output buffer switches potential on the ground line side from the first lower potential to the second lower potential after switching potential on the power supply line side from the first higher potential to the second higher potential, and returns the potential on the power supply line side to the first higher potential from the second higher potential after returning the potential on the ground line side to the first lower potential from the second lower potential.

3. The display according to claim 2 , wherein

the power supply scanner prevents voltage applied between the source and drain of the drive transistor from surpassing insulation breakdown voltage in a series of operation of the pixel by switching the higher potential applied to the power feed line between the first higher potential and the second higher potential at the different levels in the predetermined sequence.

4. An electronic apparatus comprising the display of claim 1 .

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2015
From: SONY CORPORATION
To: JOLED INC.
Reel/Frame 036106/0355 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 8, 2008
From: YAMASHITA, JUNICHI; UCHINO, KATSUHIDE
To: SONY CORPORATION
Reel/Frame 020818/0904 →