Granted Patent B2

US 8,200,887 · App. 12/079,364 · Granted Jun 12, 2012

Abstract

Claims (27)

1. A memory system, comprising:

a plurity of memory modules, each module having a FLASH memory circuit capable of writing data and reading data,

wherein data, and error correcting code data for the data, are written as a RAID stripe in a group of N memory modules of the plurality of memory modules and each module of the group of N memory modules is configured such that data is written to, or erased from, the module during a time period s, where a time period s of each of the N modules does-not fully overlap a time period s of another of the N modules.

2. The memory system of claim 1 , wherein the time periods do not substantially overlap.

3. The memory system of claim 1 , wherein the time periods of any two modules do not overlap by more than half of the time period.

4. The memory system of claim 1 , wherein when the data received from N−1 memory modules includes error correcting code data, data recoverable by computing an exclusive-OR (XOR) of the data from the N−1 modules.

5. The memory system of claim 1 , wherein the error correcting code data is computed as the exclusive-OR (XOR) of the stored data.

6. The memory system of claim 1 , wherein the time periods are non-overlapping.

7. The memory system of claim 5 , wherein the error correcting code data is distributed over the N memory modules.

8. A memory system, comprising:

a plurality of memory modules, each module having FLASH memory circuit and a timing circuit, and; and

a group K of the memory modules configured to store data including parity data, where K is a RAID stripe,

wherein each of the K memory modules is allocated a substantially non-overlapping time interval in which data may be stored to, or an erase operation performed on, the memory modules of the K memory modules.

9. The memory system of claim 8 , wherein the data received at a memory controller from any K−1 of the K memory modules of the RAID stripe may be used to represent the stored data.

10. The memory system of claim 8 , wherein the data and the parity data are distributed over the group of K memory modules.

11. The memory system of claim 8 , wherein the data from any K−1 of the K memory modules of the RAID stripe may be used to represent the stored data including the parity data.

12. The memory system of claim 8 , further comprising a memory controller communicating with the memory modules using a bus.

13. The memory system of claim 8 , wherein the time interval is at least the greater of an erase time or a write time.

14. The memory system of claim 1 , where the overlap of the time periods depends on the write or erase load of a RAID stripe.

15. The memory system of claim 1 , when data is received from any N−1 modules of the group of N memory modules, the data stored in the group of N memory modules is recoverable.

16. The memory system of claim 4 , wherein the data is received by a memory controller.

17. The memory system of claim 1 , wherein the memory module is at least one of an electronic circuit or a physical address range.

18. The memory system of claim 1 , wherein the memory module is a logical address range.

19. The memory system of claim 11 , wherein, the parity data is XORed with data from the K−1 memory modules to reconstruct missing data.

20. The memory system of claim 8 , wherein when more than a predetermined number of write or erase operations are pending for a memory module, an another time interval is also used to perform a write or erase operation.

21. The memory module of claim 20 , wherein the another time interval is offset by a different number of time intervals from the time interval at each memory module of the group of K memory modules.

22. The memory module of claim 20 , wherein the another time interval of each memory module of the K memory modules coincide in time.

Assignments (12)