Switching regulator without a dedicated input current sense element
View Patent ↗A synchronous regulator includes a controller coupled to receive a reference signal and a feedback signal from the regulator operable to provide a pulse width modulation (PWM) signal at its output. The regulator includes at least one gate driver coupled to receive the PWM signal, and a synchronous output switch having a phase node there between controlled by the gate driver, and regulator input current measurement circuitry. The regulator input current measurement circuitry comprises a circuit operable for providing a signal representative of at least one phase node timing parameter, a sensing circuit operable for sensing inductor or output current provided by the regulator, and a calculation circuit coupled to receive the signal representative of the phase node timing parameters and the inductor or output current and is operable to determine the input current.
1. A synchronous regulator, comprising:
a controller coupled to receive a reference signal and a feedback signal from said regulator operable to provide a pulse width modulation (PWM) signal at its output, at least one gate driver coupled to receive said PWM signal, and a synchronous output switch having a phase node controlled by said gate driver, and
input current measurement circuitry, comprising:
a circuit operable for providing a signal representative of at least one phase node timing parameter;
a sensing circuit operable for sensing inductor or output current provided by said regulator, and
a calculation circuit coupled to receive said signal representative of each phase node timing parameter and said inductor or output current and being operable to determine an input current to said regulator from each phase node timing parameter and the inductor or output current.
2. The regulator of claim 1 , wherein said phase node timing parameter comprises a pulse width and a pulse period at said phase node, further wherein said pulse width and said pulse period both comprise averages calculated over a plurality of pulse periods.
3. The regulator of claim 1 , wherein said circuit operable for providing a signal representative of phase node timing parameter comprises a comparator having a first input coupled to said phase node and a second input biased at a reference voltage level.
4. The regulator of claim 1 , further comprising digital circuitry coupled to receive said signal representative of phase node timing parameter and said inductor or said output current and provide average values for said phase node timing parameter and said inductor or said output current.
5. A synchronous regulator, comprising:
a controller coupled to receive a reference signal and a feedback signal from said regulator operable to provide a pulse width modulation (PWM) signal at its output, at least one gate driver coupled to receive said PWM signal, and a synchronous output switch having a phase node controlled by said gate driver, and
input current measurement circuitry, comprising:
a circuit operable for providing a signal representative of at least one phase node timing parameter;
a sensing circuit operable for sensing inductor or output current provided by said regulator, and
a calculation circuit coupled to receive said signal representative of each phase node timing parameter and said inductor or output current and being operable to determine an input current to said regulator;
digital circuitry coupled to receive said signal representative of phase node timing parameter and said inductor or said output current and provide average values for said phase node timing parameter and said inductor or said output current; and
wherein said phase node timing parameter comprises:
a pulse width and a pulse period at said phase node;
said digital circuitry comprises a first IIR filter for determining said pulse width, a second W filter for determining said pulse period, and
a third W filter for determining said average inductor or output current.
6. The regulator of claim 1 , wherein said calculation circuit comprises a multiphase sampling clock, wherein said multiphase sampling clock is operable to automatically calibrate said phase node timing parameter.
7. The regulator of claim 1 , wherein said input current provided by said digital calculation circuit is coupled to an input of said modulation controller.
8. The regulator of claim 7 , wherein said digital calculation circuit includes memory for storing an efficiency curve for said regulator versus a current supplied to said load.
9. A regulator input current measurement circuit, comprising:
a circuit operable for providing a signal representative of at least one timing parameter at a phase node of a switching regulator;
a sensing circuit operable for sensing inductor or output current provided by the regulator, and
a calculation circuit coupled to receive the signal representative of the phase node timing parameters and the inductor or output current operable to utilize the signal representative of the phase node timing parameters and the inductor or output current to determine an input current to the regulator.
10. The measurement circuit of claim 9 , wherein said circuit operable for providing a signal representative of phase node timing parameter comprises a comparator having a first input coupled to said phase node and a second input biased at a reference voltage level.
11. The measurement circuit of claim 9 , further comprising digital circuitry coupled to receive said signal representative of phase node timing parameter and said inductor or said output current and provide average values for said phase node timing parameter and said inductor or said output current.
12. The measurement circuit of claim 11 , wherein said phase node timing parameter comprises a pulse width and a pulse period at said phase node and said digital circuitry comprises a first IIR filter for determining said pulse width, a second IIR filter for determining said phase period, and a third IIR filter for determining said average inductor or output current.
13. The measurement circuit of claim 9 , wherein said digital calculation circuit includes memory for storing an efficiency curve for said regulator as a function of output current to a load driven by said regulator.
14. A system, comprising:
a synchronous regulator, comprising:
a controller coupled to receive a reference signal and a feedback signal from said regulator operable to provide a pulse width modulation (PWM) signal at its output,
at least one gate driver coupled to receive said PWM signal, and a synchronous output switch having a phase node controlled by said gate driver; and
a regulator input current measurement circuit, comprising:
a circuit operable for providing a signal representative of at least one phase node timing parameter;
a sensing circuit operable for sensing inductor or output current provided by said regulator, and
a calculation circuit coupled to receive said signal representative of said phase node timing parameters and said inductor or output current and operable from the signal and current to determine an input current to said regulator;
wherein an output of said regulator provides regulated power to at least one load.
15. The system of claim 14 , wherein said load comprises a CPU or a chip set.
16. A method for determining input current to a switching regulator, comprising:
measuring or estimating parameters comprising a pulse width at a phase node of the regulator, a pulse period at the phase node of the regulator, and an inductor current or output current provided by the regulator, and
determining an input current to the switching regulator based on these parameters.
17. The method of claim 16 , wherein said parameters comprise averages obtained over a plurality of pulse periods.
18. The method of claim 16 , wherein said pulse width and said pulse period are determined using a comparator, said comparator determining if said phase node is above or below a threshold level.
19. The method of claim 16 , further comprising averaging said pulse width, said pulse period and said inductor current or said output current using digital filtering, and using average values for said pulse width, said pulse period and said inductor current or said output current in said determining step.
20. The method of claim 19 , wherein said digital filtering comprises using separate digital filters for providing an average value of said pulse width, an average value of said pulse period, and an average value of said inductor current or said output current.
21. The method of claim 16 , wherein said determining step comprises multiplying said pulse width by said inductor current or said output current and dividing a result of said multiplying by said pulse period.
22. The method of claim 16 , further comprising the step of using said to calculate a power efficiency provided by said regulator.
23. The method of claim 16 , further comprising the step determining an actual duty cycle of said regulator and using said actual duty cycle together with a compensated ideal duty cycle for said regulator to calculate a power efficiency provided by said regulator.
24. The method of claim 23 , further comprising the step of compensating said ideal duty cycle with a first variable associated with heavy load current operation and a second variable associated with a light load current condition to provide compensated ideal duty cycle.
25. The method of claim 24 , wherein said first and second variables are programmable variables stored on an on-chip portion of said regulator.