Backplane routing arrangement with decreased crosstalk
View Patent ↗Methods of designing a backplane, a backplane, and a packet switch using such a backplane are disclosed. The backplane comprises communication channels that connect each of a set of first card slots to each of a set of second card slots. Instead of forcing the backplane to route the communication channels to match a preset card configuration, the backplane communication channels are routed so as to reduce crosstalk and attenuation on at least the most difficult routing pairs. The cards perform logical translation of their backplane traffic to conform to the physical pin assignment for the particular card slot in which they are inserted. Other embodiments are also described and claimed.
1. A method of routing differential trace pairs on an electrical backplane, comprising:
using a processor for:
identifying and storing the identities of backplane pin pairs at a first and second plurality of backplane card slots that will connect to differential trace pairs, each of the plurality of first card slots comprising at least one connector block having a pinout capable of accepting a first type of circuit card and each of the plurality of second card slots comprising at least one connector block have a pinout capable of accepting a second type of circuit card;
selecting and storing logical pairings of differential traces to connect pin pairs on the connector blocks of the first card slots to pin pairs on the connector blocks of the second card slots, such that each first card slot connects to each second card slot via at least one of the differential trace pairs; and
assigning and storing designated pin pairs to each logical pairing of differential traces, with routing priority and designated pin pair selection priority given to the logical pairings of differential traces with the longest routing distances, the assignment resulting in different pin pair assignments for at least two of the first card slots and resulting in different pin pair assignments for at least two of the second card slots.
2. The method of claim 1 , wherein assigning designated pin pairs for each logical pairing of differential traces, with routing priority and designated pin pair selection priority given to the longest routing distances, comprises:
calculating, for each logical pairing, at least one tentative best-case routing between an unassigned designated pin pair at the logical pairing first card slot and an unassigned designated pin pair at the logical pairing second card slot;
assigning at least one of the logical pairings to the designated pin pairs corresponding to its tentative best-case routing, based on a ranking of the tentative best-case routing for logical pairings that have not been assigned a routing; and
repeating calculating at least one tentative best-case routing and assigning at least one of the logical pairings for unassigned designated pin pairs and unassigned logical pairings.
3. The method of claim 2 , wherein the at least one tentative best-case routing comprises multiple possible routings, each meeting a minimum criteria, the method pruning possible routings as other logical pairings select conflicting routings.
4. The method of claim 1 , wherein the logical pairings of differential trace pair connections comprises unidirectional pairings either from one of the first card slots to one of the second card slots or from one of the second card slots to one of the first card slots, and wherein determining designated pin pairs at the first and second card slots comprises indicating whether each such pin pair is a transmit pin pair or a receive pin pair.
5. The method of claim 4 , wherein, in computing a pin pair assignment for a logical pairing, a channel model considers end-to-end channel parameters for a pin pair assignment, the end-to-end channel parameters including channel effects both on the first card, for a differential pair connecting an integrated circuit to a pin pair on the first card, and on the second card, for a differential pair connecting an integrated circuit to a pin pair on the second card.
6. The method of claim 5 , the channel parameters further comprising crosstalk parameters at least at the location of the circuit card-to-backplane connections.
7. The method of claim 6 , wherein considering the channel model comprises excluding, for two logical pairings between the same first card slot and same second card slot, the selection of pin pairs resulting in significant crosstalk between the logical pairings at both the first card slot and the second card slot.
8. The method of claim 1 , further comprising creating logical translation tables for each first and second card slot, the logical translation tables relating the pin pairs assigned to each logical pairing with the logical pairing.