Semiconductor memory device and manufacturing method thereof

1. A method for manufacturing a semiconductor memory device having a memory element in which a MOSFET and a MOS capacitor both formed in a semiconductor substrate having a semiconductor layer stacked over a support substrate through an insulating film interposed therebetween, are connected by a floating gate electrode, comprising:

setting a transistor forming area, a polygonal capacitor forming area and a device isolation area surrounding peripheries of the transistor forming area and the capacitor forming area to the semiconductor layer;

forming a device isolation layer in the device isolation area between the transistor forming area and the capacitor forming area by a LOCOS method;

forming slanting faces around the semiconductor layer of the capacitor forming area, so that a width of the semiconductor layer of the capacitor forming area increases toward the insulating film;

forming a resist mask over the semiconductor layer and the device isolation layer, the resist mask having an opening that exposes over the slanting faces formed in the semiconductor layer of a forming area of the floating gate electrode and exposes the device isolation layer lying in an area adjacent to the slanting faces;

etching the device isolation layer and the insulating film using the resist mask as a mask to form a capacitor groove which has a bottom face within the insulating film and which exposes the slanting faces;

removing the resist mask and forming a gate insulating film over the semiconductor layer including the slanting faces and the device isolation layer, and on an inner face of the capacitor groove;

forming, over the gate insulating film, a floating gate electrode which divides the transistor forming area into two and extends over a corner of the capacitor forming area on a transistor forming area side; and

ion-implanting an impurity of a same type as an impurity diffused into a source layer of the MOSFET into the semiconductor layer lying on both sides of the floating gate electrode of the transistor forming area and into the semiconductor layer of the capacitor forming area to form the source layer of the MOSFET, a drain layer thereof and a capacitor electrode of the MOS capacitor.

2. The method according to claim 1 , wherein the capacitor forming area has a mountain portion which protrudes toward the transistor forming area, and

wherein the floating gate electrode is formed so as to extend over a corner of a top of the mountain portion.

3. The method according to claim 1 , wherein the capacitor forming area is set to a rectangular polygon, and

wherein the floating gate electrode is formed so as to extend over one corner on the transistor forming area side, of the capacitor forming area.

4. The method according to claim 1 , wherein the capacitor forming area is set to a rectangular polygon, and

wherein the floating gate electrode is formed so as to extend over both corners on the transistor forming area side, of the capacitor forming area.

5. The method according to claim 1 , wherein the capacitor groove is formed to undercut the slanting faces.

6. The method according to claim 1 , wherein said forming slanting faces further includes forming slanting faces around the semiconductor layer of the transistor forming area, so that a width of the semiconductor layer of the transistor forming area increases toward the insulating film.

7. The method according to claim 6 , wherein the capacitor groove is formed to undercut the slanting faces.