High-voltage transistor and component containing the latter

1. A high-voltage NMOS transistor with a low threshold voltage, with a semiconductor substrate in which a source region and a drain region are respectively produced in the form of an n+-doped region on both sides of a channel region that is arranged vertically underneath a gate electrode,

wherein the channel region is defined by a deep p-well in the semiconductor substrate, and wherein an additional shallow p-doping operating as a channel stopper at the transistor head is arranged in the semiconductor substrate at the end of the deep p-well that faces away from the channel region, and the channel stopper extends as far as a location underneath a field oxide region that encloses a first active region,

wherein the source region is in the first active region, wherein the drain region is in a second active region,

wherein the first active region comprises a first boundary proximal to the second active region, an opposite second boundary distal to the second active region, and lateral boundaries arranged between the first and second boundaries, and wherein the channel stopper is arranged at at least one of the lateral boundaries, and

wherein the deep p-well is arranged symmetrically between the source region and the drain region, wherein the shallow p-doping is arranged within the deep p-well and delimits the channel region on the transistor head on both sides, wherein the gate electrode features a lateral narrowing section in the area disposed above of the channel region and increases in width on both sides of the lateral narrowing section, wherein the deep p-well transversely intersects the at least a portion of the channel region proximal to the lateral narrowing section of the gate electrode, and wherein the shallow p-doping on the transistor head is partially arranged underneath the lateral narrowing section of the gate electrode.

2. The transistor according to claim 1 , wherein the shallow p-doping is only partially embedded in the deep p-well.

3. The transistor according to claim 1 , wherein a shallow n-well is embedded in a deep n-well in the drain region, and wherein the deep n-well extends in the form of a drift region from the drain region to a location underneath the gate electrode of them transistor and borders on the channel region.

4. The transistor according to claim 3 , wherein the source region is symmetrical to the drain region.

5. An electronic semiconductor component with a transistor according to claim 1 , further comprising at least one high-voltage PMOS transistor, wherein a drift zone in the high-voltage PMOS transistor shares the same deep p-well as the doping of the channel region of the high-voltage NMOS transistor.

6. An electronic semiconductor component with a transistor according to claim 1 , further comprising at least one low-voltage transistor of the NMOS type, the channel region of which is comprised of the same shallow p-doping as the channel stopper of the HV-NMOS, wherein the shallow p-doping of the low-voltage transistor is also embedded in a deep p-well.

7. A method for manufacturing a semiconductor component with a high-voltage NMOS transistor and a high-voltage PMOS transistor, comprising:

performing an implantation of dopant in order to produce a deep p-well that forms a drift zone for the high-voltage PMOS transistor and a channel region for the high-voltage NMOS transistor; and

performing an implantation of dopant in order to produce an additional shallow p-well that forms part of a drain doping for the high-voltage PMOS transistor and a channel stopper for the high-voltage NMOS transistor in a region that laterally defines the channel region,

wherein a channel region for a low-voltage NMOS transistor is produced with the implantation of the shallow p-well, and wherein the shallow p-well is embedded in a deep p-well in the low-voltage NMOS transistor,

wherein the shallow p-well extends as far as a location vertically underneath a field oxide region that encloses a first active region, wherein a source region is in the first active region, wherein a drain region is in a second active region, wherein the first active region comprises a first boundary proximal to the second active region, an opposite second boundary distal to the second active region, and lateral boundaries arranged between the first and second boundaries, and wherein the channel stopper is arranged at least one of the lateral boundaries, and

wherein the deep p-well is arranged symmetrically between the source region and the drain region, wherein the shallow p-well is arranged within the deep p-well and delimits the channel region on the transistor head on both sides, wherein the gate electrode features a lateral narrowing section in the area disposed above of the channel region and increases in width on both sides of the lateral narrowing section, wherein the deep p-well transversely intersects the at least a portion of the channel region proximal to the lateral narrowing section of the gate electrode, and wherein the shallow p-well on the transistor head is partially arranged underneath the lateral narrowing section of the gate electrode.

8. The method according to claim 7 , wherein the channel stopper is arranged within the deep p-well.

9. The method according to claim 7 , wherein the channel region in the low-voltage NMOS transistor is produced with two interlaced implantations, and wherein the deep p-well is also provided for the channel region of the high-voltage NMOS transistor and the shallow p-well embedded therein corresponds to the shallow p-doping for the channel stopper of the high-voltage NMOS transistor.