Device and method for managing a retransmit operation
View Patent ↗A method and device for managing retransmit operations. The device, includes a FIFO memory unit, a read pointer, a retry pointer and a write pointer. The device is characterized by including a gray code state machine connected to an emulated read pointer logic; whereas the gray code state machine is adapted to provide a gray code word representative of a state of a read logic that comprises the read pointer; whereas the emulated read pointer logic is adapted to process at least one gray code word and to provide an emulated read pointer that tracks a FIFO memory unit entry that stores data that was not accepted; whereas the emulated read pointer logic is connected to a write control logic adapted to control writing operations to the FIFO memory unit in response to the emulated read pointer logic; and whereas the read logic receives a read clock that differs from a write clock provided to the emulated read pointer logic and to the write control logic.
1. A device comprising:
a FIFO memory unit, a read pointer, a retry pointer and a write pointer;
a gray code state machine coupled to an emulated read pointer logic;
whereas the gray code state machine is adapted to provide a gray code word representative of a state of a read logic that comprises the read pointer;
whereas the emulated read pointer logic is adapted to process at least one gray code word and to provide an emulated read pointer that tracks a FIFO entry that stores data that was not accepted; and
whereas the emulated read pointer logic is coupled to a write control logic adapted to control writing operations to the FIFO memory unit in response to the emulated read pointer logic.
2. The device according to claim 1 whereas the emulated read pointer logic is adapted to compare between a current gray code word and a previous gray code word.
3. The device according to claim 1 , whereas the write control logic is adapted to provide a FIFO full indication.
4. The device according to claim 1 , whereas the write control logic is adapted to provide an indication about the number of empty FIFO memory unit entries.
5. The device according to claim 1 , further adapted to read a multiple byte data word from a FIFO memory unit entry to an intermediate buffer and to sequentially send portions of the multiple byte data word to the data target.
6. The device according to claim 1 , whereas the read logic comprises a retry pointer and the emulated read pointer logic comprises a shadow counter.
7. The device according to claim 1 , whereas the emulated read pointer represents a first FIFO memory unit entry that stores data that was not accepted.
8. The device according to claim 1 , whereas the read logic receives a read clock that differs from a write clock provided to the emulated read pointer logic and to the write control logic.
9. The device according to claim 1 , wherein the device is adapted to re-transmit data from the FIFO memory unit.
10. A method that comprises;
receiving, by a read logic, read status information;
providing to a read logic a read clock and providing to a write logic a write clock;
generating a gray code word representative of the read status information by a read logic;
processing, by the write logic, at least one gray code word to provide an emulated read pointer that tracks a FIFO memory unit entry that stores data that was not accepted; and
controlling write operations to the FIFO in response to a comparison between the emulated read pointer and a write pointer.
11. The method according to claim 10 whereas the stage of processing comprises comparing between a current gray code word and a previous gray code word.
12. The method according to claim 10 , whereas the controlling comprises providing a FIFO full indication.
13. The method according to claim 10 , whereas the controlling comprises providing an indication of a number of empty FIFO memory unit entries.
14. The method according to claim 10 , further comprising reading a multiple byte data word from a FIFO memory unit entry to an intermediate buffer and sequentially sending portions of the multiple byte data word to the data target.
15. The method according to claim 10 , whereas the controlling comprises updating a shadow counter.
16. The method according to claim 10 , whereas the stage of processing comprises providing an emulated read pointer that points to a first FIFO memory unit entry that stores data that was not accepted.
17. The method according to claim 10 , whereas the read clock differs from the write clock.
18. The method according to claim 10 , further comprises re-transmitting information from the FIFO memory unit.
19. The method according to claim 11 , whereas the controlling comprises providing a FIFO full indication.
20. The method according to claim 11 , whereas the controlling comprises providing an indication of a number of empty FIFO memory unit entries.