Semiconductor device
View Patent ↗A technique capable of improving speed of a set operation, which controls writing rate in a semiconductor device including a memory cell using a phase-change material. The technique uses means for setting a set-pulse voltage to be applied to the phase-change material to have two steps: the first-step voltage sets a temperature of the phase-change memory to a temperature at which the fastest nucleation is obtained; and the second pulse sets the temperature to a temperature at which the fastest crystal growth is obtained, thereby obtaining solid-phase growth of the phase-change material without melting. Moreover, the technique uses means for controlling the two-step voltage applied to the phase-change memory by a two-step voltage applied to a word line capable of reducing the drain current variation.
1. A semiconductor device comprising a plurality of word lines, a plurality of bit lines, and memory cells provided at predetermined cross points of the plurality of word lines and the plurality of bit lines, the memory cell including a phase-change material and a selection element,
wherein the semiconductor device has: a function to apply a voltage that is lower than a voltage amorphousizing the phase-change material of a reset operation, takes a shorter time to reach a crystallization temperature from a start of pulse application than a time of proceeding crystallization, and causes the phase-change material to eventually reach its melting point if maintain the voltage applied to the phase-change memory, thereby increasing a temperature of the phase-change material; and a function to stop application of the voltage before reaching the melting point, thereby cooling the phase-change material, in a set operation for crystallizing the phase-change material.
2. The semiconductor device according to claim 1 ,
wherein the selection element is a MIS transistor.
3. The semiconductor device according to claim 1 ,
wherein the selection element is a bipolar transistor.
4. The semiconductor device according to claim 1 ,
wherein the phase-change material contains at least Te.
5. A semiconductor device comprising a plurality of word lines, a plurality of bit lines, and memory cells provided at predetermined cross points of the plurality of word lines and the plurality of bit lines, the memory cell including a phase-change material and a selection element,
wherein, the semiconductor device has a function to apply a first voltage to the phase-change material, thereby increasing a temperature of the phase-change material to a temperature lower than a melting point; and a function to apply a second voltage that is lower than the first voltage and applied for a shorter application time than an application time of the first voltage to the phase-change material, thereby changing the temperature of the phase-change material to a temperature lower than the temperature reached by the first voltage application, in a set operation for crystallizing the phase-change material.
6. The semiconductor device according to claim 5 ,
wherein the change from the first voltage to the second voltage is controlled by a change of a voltage applied to the word line.
7. The semiconductor device according to claim 5 ,
wherein the change from the first voltage to the second voltage is controlled by a change of a voltage applied to the bit line.
8. The semiconductor device according to claim 5 ,
wherein the temperature of the phase-change material reached by the application of the first voltage is substantially identical to a temperature at which a nucleation velocity becomes maximum.
9. The semiconductor device according to claim 5 ,
wherein the temperature of the phase-change material reached by the application of the second voltage is substantially identical to a temperature at which a crystal growth velocity becomes maximum.
10. The semiconductor device according to claim 5 ,
wherein the selection element is a MIS transistor.
11. The semiconductor device according to claim 5 ,
wherein the selection element is a bipolar transistor.
12. The semiconductor device according to claim 5 ,
wherein the phase-change material contains at least Te.
13. A semiconductor device comprising:
a plurality of word lines;
a plurality of bit lines crossing the plurality of word lines;
a plurality of memory cells provided at cross points of the plurality of word lines and the plurality of bit lines; and
a control circuit that controls a write pulse to the plurality of memory cells,
wherein the control circuit includes a first shot-pulse generation circuit that outputs a first control signal and a second shot-pulse generation circuit that outputs a second control signal, and
wherein, when writing is performed on any of the plurality of memory cells, the first shot-pulse generation circuit causes a transition of a potential of the first control signal to a selection level to change a potential of the write pulse to a first selection level, and then the second shot-pulse generation circuit causes a transition of a potential of the second control signal to a selection level to change the potential of the write pulse from the first selection level to a second selection level.
14. The semiconductor device according to claim 13 , further comprising a plurality of drivers that supply the write pulse to the plurality of memory cells,
wherein each of the plurality of drivers includes a first MOS transistor having a source and a drain between a first potential corresponding to the first selection level and an output node that outputs the write pulse, and a second MOS transistor having a source and a drain between a second potential corresponding to the second selection level and the output node, and
the first control signal is inputted to a gate of the first MOS transistor, and the second control signal is inputted a gate of the second MOS transistor.
15. The semiconductor device according to claim 14 ,
wherein the second potential is higher than the first potential.
16. The semiconductor device according to claim 14 ,
wherein a transition period of the first control signal from the selection level to a non-selection level and a transition period of the second control signal from the selection level to a non-selection level overlap each other.
17. The semiconductor device according to claim 14 ,
wherein the control circuit outputs a third control signal for causing the write pulse to be at a non-selection level,
each of the plurality of drivers further includes a third MOS transistor having a source and a drain between a third potential corresponding to the non-selection level and the output node, and
the third control signal is inputted to a gate of the third MOS transistor.
18. The semiconductor device according to claim 14 ,
wherein the output node is connected to a corresponding one of the plurality of word lines.
19. The semiconductor device according to claim 13 ,
wherein each of the plurality of memory cells has a phase-change resistor.