Data processing arrangement comprising a reset facility
View Patent ↗A data processing arrangement (MPS) comprises a plurality of data processors (SPR, PM 1 , . . . , PM 4 ) that can be reset individually. A reset module (RSM) handles various reset request signals (HRG, SRG, SRP 1 , . . . , SRP 4 ) in accordance with a prioritization and timing scheme so as to obtain respective reset signals (GRS, PRS 1 , . . . , PRS 4 ) for respective data processors (SPR, PM 1 , . . . , PM 4 ). The reset module (RSM) preferably comprises a reset request register, which stores respective reset requests that the respective reset request signals convey, and a request execute register, which stores respective granted reset requests that the reset signals convey.
1. A data processing arrangement comprising:
a plurality of data processors that can be reset individually; and
a reset module for handling various reset request signals for each of the data processors in accordance with a prioritization and timing scheme so as to obtain respective reset signals for respective data processors, wherein the reset module is separate from each of the data processors for centralized handling of the reset request signals for each of the data processors, wherein the reset module comprises:
a reset request register;
a reset handling module; and
a reset execute resister; and
wherein the reset request register is configured to store a reset request signal for each of the data processors and to provide the stored reset request signals to the reset handling module.
2. The data processing arrangement according to claim 1 , the reset module being arranged to handle the respective reset request signals on the basis of at least one status signal, which indicates a state within the data processing arrangement.
3. The data processing arrangement according to claim 1 , the reset module comprising an assembly of hardware logic circuits that define the prioritization and timing scheme.
4. The data processing arrangement according to claim 1 , the reset module comprising a programmable hardware logic circuit that defines the prioritization and timing scheme.
5. An apparatus comprising a data-processing arrangement according to claim 1 .
6. An apparatus according to claim 5 , further comprising a transmitter-and-receiver circuit, the data-processing arrangement being arranged to process a signal from the transmitter-and-receiver circuit.
7. The data processing arrangement according to claim 1 , wherein the reset handling module is configured to generate granted reset request signals in response to the stored reset request signals and to output the granted reset request signals to the reset execute register.
8. The data processing arrangement according to claim 7 , wherein the reset execute register is configured to store the granted reset request signals and to provide the stored and granted reset request signals to respective ones of the data processors.
9. The data processing arrangement according to claim 8 , wherein the reset module comprises an assembly of hardware logic circuits that define the prioritization and timing scheme.
10. The data processing arrangement according to claim 8 , wherein the reset module comprises a programmable hardware logic circuit that defines the prioritization and timing scheme.
11. The data processing arrangement according to claim 8 , wherein the reset request register includes a different storage register for each of the data processors and wherein the reset execute register includes a different storage register for each of the data processors.
12. The data processing arrangement according to claim 11 , wherein the reset request register includes a storage register for an incoming hardware global reset signal and a storage register for an incoming software global reset signal and wherein the reset execute register includes a storage register for an outgoing hardware global reset signal and a storage register for an outgoing software global reset signal.
13. A data processing arrangement comprising:
a plurality of data processors that can be reset individually; and
a reset module for handling various reset request signals for each of the data processors in accordance with a prioritization and timing scheme so as to obtain respective reset signals for respective data processors, wherein the reset module comprises a reset request register, a reset handling module, and a reset execute resister;
wherein the reset request register is configured to store a reset request signal for each of the data processors and to provide the stored reset request signals to the reset handling module;
wherein the reset handling module is configured to generate granted reset request signals in response to the stored reset request signals and to output the granted reset request signals to the reset execute register; and
wherein the reset execute register is configured to store the granted reset request signals and to provide the stored and granted reset request signals to respective ones of the data processors.
14. The data processing arrangement according to claim 13 , wherein the reset request register includes a different storage register for each of the data processors and wherein the reset execute register includes a different storage register for each of the data processors.
15. The data processing arrangement according to claim 14 , wherein the reset request register includes a storage register for an incoming hardware global reset signal and a storage register for an incoming software global reset signal and wherein the reset execute register includes a storage register for an outgoing hardware global reset signal and a storage register for an outgoing software global reset signal.
16. An apparatus comprising:
a transmitter-and-receiver circuit configured to generate a demodulation signal in response to a received radio frequency signal; and
a data-processing arrangement configured to process the demodulation signal from the transmitter-and-receiver circuit, the data-processing arrangement comprising:
a plurality of data processors that can be reset individually; and
a reset module for handling various reset request signals for each of the data processors in accordance with a prioritization and timing scheme so as to obtain respective reset signals for respective data processors, wherein the reset module comprises a reset request register, a reset handling module, and a reset execute resister;
wherein the reset request register is configured to store a reset request signal for each of the data processors and to provide the stored reset request signals to the reset handling module;
wherein the reset handling module is configured to generate granted reset request signals in response to the stored reset request signals and to output the granted reset request signals to the reset execute register; and
wherein the reset execute register is configured to store the granted reset request signals and to provide the stored and granted reset request signals to respective ones of the data processors.
17. The data processing arrangement according to claim 16 , wherein the reset request register includes a different storage register for each of the data processors and wherein the reset execute register includes a different storage register for each of the data processors.
18. The data processing arrangement according to claim 17 , wherein the reset request register includes a storage register for an incoming hardware global reset signal and a storage register for an incoming software global reset signal and wherein the reset execute register includes a storage register for an outgoing hardware global reset signal and a storage register for an outgoing software global reset signal.