Alignment and deskew for multiple lanes of serial interconnect
View Patent ↗Methods and apparatus are provided for data communication between a transmitter and receiver over a plurality of serial links, which cause the transmitter to send serialized groups of bits down each lane, in such a way that the first bit of each group (each lane) is guaranteed to arrive in the correct order at the receiving end. Various embodiments of the present invention include declaring a budget for the maximum skew between lanes. In such embodiments, subsequent to determining the skew budget between lanes, the data to be transmitted is divided into groups of N bits, where N is any convenient number larger than M times S, with M being the number of lanes and S being the budgeted skew, in bit times.
1. A method of transmitting data between a transmitter having data to send, and a receiver, comprising:
determining a skew budget between a plurality of serial links disposed between the transmitter and receiver;
determining a number of bits N, where N is an integer greater than M×S, where M is the number of serial links, and S is the skew budget in bit times;
capturing, in a circuit and in response to determining N, a first N bits of the data to be sent;
beginning the transmission of the first N bits on a first one of the plurality of serial links;
capturing, in a circuit and in response to determining N, a second N bits of the data; and
transmitting the second N bits of data at approximately N/M bit times subsequent to the beginning of the transmission on the first one of the plurality of serial links, and beginning the transmission of the second N bits on a second one of the plurality of serial links.
2. The method of claim 1 , wherein capturing the first N bits comprises accessing a memory disposed within the transmitter and serializing the first N bits.
3. The method of claim 2 , wherein capturing the second N bits comprises accessing the memory disposed within the transmitter and serializing the second N bits.
4. The method of claim 1 , further comprising the first N bits and the second N bits at the receiver.
5. The method of claim 1 , further comprising capturing and transmitting additional groups of N bits on sequentially designated lanes, the beginnings of the transmissions being separated by N/M bit times, until all the data to be sent has been transmitted.
6. The method of claim 1 , further including the step of determining a value for M×S and wherein the step of determining a number of bits N is in response to the value for M×S.
7. The method of claim 6 , wherein the step of determining the number of bits N includes selecting an integer value that is both a multiple of 8 and that is greater than the determined value of M×S.
8. The method of claim 6 , wherein determining N includes dividing the data to be transmitted into groups of N bits.
9. The method of claim 6 , wherein the skew budget S is determined by reference to a dynamically updatable table.
10. The method of claim 6 , further including the steps of
accessing a preprogrammed value representing the skew budget between the serial links, and
using the preprogrammed value as the skew budget S.
11. The method of claim 6 , further including the step of delaying the sending the second N bits of data until after a period of at least N/M bit times have elapsed subsequent to sending the first N bits of data.
12. A transmitter adapted for use with a plurality of serial links, comprising:
a packet memory operable to store packets for transmission, the packet memory producing a multi-bit output when accessed; and
a data processing circuit configured for
determining a skew budget the plurality of serial links;
determining a number of bits N, where N is greater than M×S, where M is the number of serial links, and S is the skew budget in bit times;
capturing a first N bits of the data to be sent, and beginning the transmission of the first N bits on a first one of the plurality of serial links; and
capturing a second N bits of the data to be sent, at approximately N/M bit times subsequent to the beginning of the transmission on the first one of the plurality of serial links, and beginning the transmission of the second N bits on a second one of the plurality of serial links.
13. The transmitter of claim 12 , wherein the data processing circuit is further configured for accessing the packet memory and serializing the first N bits.
14. The transmitter of claim 13 , wherein the data processing circuit is further configured for accessing the packet memory and serializing the second N bits.
15. A method of transmitting data between a transmitter and a receiver over a plurality of serial links, comprising:
a) determining a skew between the serial links, the serial links between the transmitter and the receiver;
b) determining a number, N, where N is greater than M times S, M is the number of serial links, and S the skew;
c) capturing, in a circuit, N bits from a transmit buffer;
d) begin transmitting the captured N bits on a serial link designated by a serial link pointer;
e) updating the serial link pointer;
f) capturing a next N bits from the transmit buffer;
g) determining whether N/M bit times have elapsed since the beginning of the last transmission;
h) determining whether there is more data to be sent;
i) repeating steps (d) through (h).
16. The method of claim 15 , wherein determining a skew between links comprises referring to a table.
17. The method of claim 16 , wherein the table is disposed external to an integrated circuit on which the transmitter is disposed.
18. The method of claim 15 , wherein capturing N bits comprises reading from a memory and serializing the data.
19. The method of claim 15 , wherein updating the serial link pointer comprises incrementing a counter.
20. The method of claim 15 , wherein N is a multiple of 8.