Subharmonically pumped mixer
View Patent ↗The present invention relates to a sub-harmonically pumped conversion mixer arrangement that includes a transistor arrangement and transistor terminals for application of a local oscillator, LO-, signal and application of a radio frequency, RF-, signal and for extraction of a mixed intermediate frequency, IF-, signal. The transistor arrangement includes at least one NMOS transistor and at least one PMOS transistor. The drain of the at least one NMOS transistor is interconnected with the drain of the at least one PMOS transistor, and in that the gate of the at least one PMOS transistor is interconnected with the gate of the at least one NMOS transistor.
1. A sub-harmonically pumped conversion mixer arrangement comprising:
a transistor arrangement and transistor terminals for application of a local oscillator (LO) signal and receiving and extracting a radio frequency (RF) signal and for receiving and extracting a mixed intermediate frequency (IF) signal, the transistor arrangement further comprising:
at least one NMOS transistor and at least one PMOS transistor, the drain of said at least one NMOS transistor being interconnected with the drain of said at least one PMOS transistor and the gate of said at least one PMOS transistor being interconnected with the gate of said at least one NMOS transistor, wherein the source of the PMOS transistor is interconnected with the source of the NMOS transistor;
and wherein the transistor arrangement comprises three separate transistor terminals, a gate terminal, a source terminal and a drain terminal, the terminals being adapted to provide a separate port for each of the LO, RF and IF signals respectively.
2. The mixer arrangement according to claim 1 , being passive wherein the sources of the NMOS and PMOS transistors are one selected from (i) being not biased or (ii) biasing means are provided for equally biasing the sources of the NMOS and the PMOS transistors, or (iii) there is no DC-voltage difference between source and drain of the respective PMOS and NMOS transistors.
3. The mixer arrangement according to claim 1 , being active wherein biasing means are provided for one of (i) biasing the source of the PMOS transistor independently or differently from the source of the NMOS transistor, or (ii) biasing only the source of the PMOS transistor or the source of the NMOS transistor respectively, or (iii) the sources are biased such that there is a DC-voltage difference between the drain and source of the respective PMOS and NMOS transistors.
4. The mixer arrangement according to claim 3 , wherein biasing means are provided for biasing the gates of the PMOS and NMOS transistors independently and/or differently.
5. The mixer arrangement according claim 1 used as a down-conversion mixer for extraction of the IF signal at the transistor terminal formed at the interconnected drains used as an IF port.
6. The mixer arrangement according to claim 5 , wherein the source terminal of the transistor arrangement is used as an LO signal port for application of the LO signal and in that the gate terminal is adapted to be used as an RF signal port.
7. The mixer arrangement according to claim 5 , wherein the source terminal of the transistor arrangement is used as an RF signal port and the gate terminal is used as an LO signal port.
8. The mixer arrangement according to claim 1 , wherein the interconnected gates form a gate terminal used as a single signal port.
9. The mixer arrangement according to claim 1 wherein the gate terminal is used as an RF signal port for application of an RF signal.
10. The mixer arrangement according to claim 1 , wherein signal filters and/or impedance matching means are coupled to one or more of the transistor terminals.
11. The mixer arrangement according claim 1 further comprising impedance means provided at the interconnected sources, said impedance means setting a DC level, ground or other appropriate level and to provide for AC-signal separation therefrom, having a high AC impedance and a low DC impedance, said impedance means optionally comprising impedance matching means.
12. The mixer arrangement according to claim 1 further comprising an IF filter provided at the terminal acting as an IF port operable to filter out unwanted mixer products from the desired signal.
13. The mixer arrangement according to claim 12 , wherein the IF filter comprises a low pass filter.
14. The mixer arrangement according claim 13 , wherein the filter means and/or impedance matching means are provided at one or more of the terminals.
15. The mixer arrangement according claim 1 , configured as an up-conversion mixer.
16. The mixer arrangement according to claim 15 , wherein a transistor terminal is formed at the interconnected drains and in that said drain terminal extracts the RF signal.
17. The mixer arrangement according to claim 15 , further comprising impedance means coupled to the sources to set a DC-level and in that it comprises a high AC impedance and a low DC-impedance and optionally an impedance matching functionality.
18. The mixer arrangement according to claim 1 , wherein the gate terminal acts as an IF port for receiving the IF signal and in that the source terminal acts as an LO port for receiving the LO signal.
19. The mixer arrangement according to claim 1 , wherein the gate terminal acts as an LO port for receiving the LO signal and the source terminal acts as an IF port for receiving the IF signal.
20. The mixer arrangement according to claim 1 , implemented as a Monolithic Microwave Integrated circuit (MMIC).
21. The mixer arrangement according to claim 1 , for handling RF and LO signals in the microwave frequency region.
22. The mixer arrangement according to claim 1 , for handling RF and LO-signals in the millimeter wave frequency region.