Communication scheme between programmable sub-cores in an emulation environment

1. In an emulation environment, a communication scheme in a programmable core used to emulate a hardware design of a user, comprising:

multiple programmable sub-cores within the programmable core, the programmable core being within a single integrated circuit; and

a network, within the same integrated circuit, coupled between the programmable sub-cores for communication there between, the network including at least one multiplexer associated with a first of the programmable sub-cores and at least one demultiplexer associated with a second of the programmable subcores, wherein the programmable core is an FPGA positioned on a single semiconductor die within the integrated circuit and the network is for communication between sub-cores within the FPGA, wherein the network is without a crossbar switch.

2. The emulation environment of claim 1 , wherein the network further includes a clock coupled to the multiplexer and demultiplexer for synchronization there between.

3. The emulation environment of claim 1 , wherein each programmable sub-core includes a programmable portion for programming the hardware design that can only communicate with other sub-cores through the network.

4. The emulation environment of claim 1 , further including an I/O portion in the network that includes multiple multiplexers for sending messages over the network and multiple demultiplexers for receiving messages from the network.

5. The emulation environment of claim 1 , wherein the multiplexer and demultiplexer are not part of the hardware design of the user.

6. A method of communicating in a programmable core of an emulation environment, comprising:

programming multiple programmable sub-cores in a single integrated circuit with a user design to be emulated; and

communicating between the multiple programmed sub-cores over a multiplexer-based network, wherein the single integrated circuit is an FPGA positioned on a single semiconductor die with the sub-cores communicating within the FPGA, wherein the network includes a clock coupled to the multiplexer and demultiplexer to synchronize communication there between.

7. The method of claim 6 , wherein communicating over the network includes multiplexing a signal from one of the programmed sub-cores onto a signal line and demultiplexing the signal in another of the programmed sub-cores.

8. The method of claim 6 , wherein the communication between programmable cores occurs without traversing a crossbar switch.

9. The method of claim 6 , further including receiving a clock signal in an I/O portion of the network to synchronize communication in the multiplexer-based network.

10. The method of claim 9 , wherein the I/O portion includes multiplexers and demultiplexers that are not part of the user design.

11. An emulator, comprising:

multiple printed circuit boards coupled together through a mid-plane or back-plane;

multiple integrated circuits positioned on each of the printed circuit boards;

an FPGA core within at least one of the integrated circuits;

multiple sub-cores within the FPGA core, the sub-cores including a programmable portion;

a network coupled between the multiple sub-cores, the network including a multiplexer associated with one of the sub-cores and a corresponding demultiplexer coupled to the multiplexer on another of the sub-cores, wherein the network includes a clock coupled to the multiplexer and demultiplexer to synchronize communication there between.