High voltage power regulation using two power switches with low voltage transistors
View Patent ↗A switching regulator having first and second power switches. The first power switch has at least two transistors connected in series, the transistors having a first maximum voltage across their terminals which is less than the input voltage of the regulator. The transistors have at least a first node at the point where they are connected, and a first control circuit controls the voltage at the first node so that the voltages across the terminals of the transistors of the first power switch do not exceed the first maximum voltage. The second power switch also has at least two transistors connected in series, the transistors having a maximum voltage across their terminals that is less than the input voltage. The transistors have at least a second node at the point where they are connected, and a second control circuit controls the voltage at the second node so that the voltages across the terminals of the transistors of the second power switch do not exceed the second maximum voltage.
1. A switching regulator for receiving an input voltage and comprising:
a first power switch including:
at least two transistors connected in series, the transistors having at least a first node where two of the transistors are connected; and
at least a first control circuit configured to set a voltage at the first node to a first intermediate voltage when the first power switch is turned off, wherein the first control circuit includes a first switch configured to connect a gate terminal and a conduction terminal of one of the at least two transistors of the first power switch; and
a second power switch including:
at least two transistors connected in series, the transistors having at least a second node where two of the transistors are connected; and
at least a second control circuit configured to set a voltage at the second node to a second intermediate voltage when the second power switch is turned off.
2. The switching regulator of claim 1 wherein the first power switch is connected between an input of the switching regulator and a third node and the second power switch is connected between a common voltage and the third node.
3. The switching regulator of claim 1 wherein the conduction terminal is a source terminal.
4. The switching regulator of claim 1 wherein the second control circuit includes a second switch configured to connect a gate terminal and a source terminal of one of the series connected transistors of the second power switch.
5. The switching regulator of claim 1 wherein the series-connected transistors of the first power switch have a first maximum permitted voltage across their terminals which is less than the input voltage of the switching regulator, the first intermediate voltage being greater than or equal to the input voltage less the first maximum permitted voltage.
6. The switching regulator of claim 5 wherein the series-connected transistors of the second power switch have a second maximum permitted voltage across their terminals which is less than the input voltage of the switching regulator, the second intermediate voltage being less than or equal to the second maximum permitted voltage.
7. The switching regulator of claim 6 wherein the first intermediate voltage equals the input voltage less the second intermediate voltage.
8. The switching regulator of claim 1 wherein one of the series connected transistors of the first power switch has a gate terminal which is configured to switch the one of the series connected transistors on during a period of time while another of the series connected transistors of the first power switch has a gate terminal which is configured to switch the other of the series connected transistors off.
9. The switching regulator of claim 8 wherein the first switch is configured to connect the gate terminal to the source terminal of the non-switched series connected transistor of the first power switch.
10. The switching regulator of claim 1 wherein the at least two transistors of the first power switch connected in series include a first transistor and a second transistor, a gate terminal of the first transistor being switched between the input voltage and the first intermediate voltage and a gate terminal of the second transistor being fixed at the first intermediate voltage, wherein the first control circuit is configured to utilize a third transistor to electrically connect the first node to the first intermediate voltage.
11. The switching regulator of claim 10 wherein the at least two transistors of the second power switch connected in series include a fourth transistor and a fifth transistor, a gate terminal of the fourth transistor being switched between ground and the second intermediate voltage and a gate terminal of the fifth transistor being fixed at the second intermediate voltage, wherein the second control circuit is configured to utilize a sixth transistor to electrically connect the second node to the second intermediate voltage.
12. A power supply circuit comprising:
a switching regulator, including:
a first power switch including:
at least two transistors connected in series, the transistors having at least a first node where two of the transistors are connected; and
at least a first control circuit configured to set a voltage at the first node to a first intermediate voltage when the first power switch is turned off, wherein the first control circuit includes a first switch configured to connect a gate terminal and a conduction terminal of one of the at least two transistors of the first power switch; and
a second power switch including:
at least two transistors connected in series, the transistors having at least a second node where two of the transistors are connected; and
at least a second control circuit configured to set a voltage at the second node to a second intermediate voltage when the second power switch is turned off;
a control signal generator for providing signals for switching at least one of the transistors of each of the power switches of the switching regulator; and
an internal power supply for providing the first and second intermediate voltages.
13. An audio power amplifier circuit comprising:
a switching regulator, including:
a first power switch including:
at least two transistors connected in series, the transistors having at least a first node where two of the transistors are connected; and
at least a first control circuit configured to set a voltage at the first node to a first intermediate voltage when the first power switch is turned off, wherein the first control circuit includes a first switch configured to connect a gate terminal and a conduction terminal of one of the at least two transistors of the first power switch; and
a second power switch including:
at least two transistors connected in series, the transistors having at least a second node where two of the transistors are connected; and
at least a second control circuit configured to set a voltage at the second node to a second intermediate voltage when the second power switch is turned off;
a control signal generator for providing signals for switching at least one of the transistors of each of the power switches of the switching regulator; and
an internal power supply for providing the first and second intermediate voltages.
14. A method for operating a switching regulator having an input voltage, the switching regulator comprising first and second power switches each comprising at least two transistors connected in series, the transistors having an upper gate to source threshold voltage across each transistor's terminals which is less than the input voltage, the transistors in the first power switch having a first node where two of the transistors are connected, and the transistors in the second power switch having a second node where two of the transistors are connected, comprising:
setting the voltage at the first node to a first intermediate voltage when the first power switch is turned off, so that the voltages across each transistor's terminals of the first power switch do not exceed the upper gate to source threshold voltage; and
setting the voltage at the second node to a second intermediate voltage when the second power switch is turned off, so that the voltages across each transistor's terminals of the second power switch do not exceed the upper gate to source threshold voltage, wherein setting the voltage at the first node includes utilizing an intermediate switch to couple a gate terminal of one of the transistors of the first power switch to a conduction terminal of another of the transistors of the first power switch.
15. The method of claim 14 wherein the first intermediate voltage is greater than or equal to the input voltage less the upper gate to source threshold voltage.
16. The method of claim 14 wherein the second intermediate voltage is less than or equal to the upper gate to source threshold voltage.
17. The method of claim 14 wherein the first intermediate voltage equals the input voltage less the second intermediate voltage.