IP Library Granted Patent US 7,605,740
Granted Patent B2
US 7,605,740 · App. 12/097,040 · Granted Oct 20, 2009

Flash analog-to-digital converter

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Quick Facts
Patent No.
US 7,605,740
App. No.
12/097,040
Granted
Oct 20, 2009
Kind
B2
Abstract

A flash analog-to-digital converter comprises a resistive string powered by a reference voltage source for providing a set of equidistant reference voltages and a set of comparators for comparing the analog input signal with the reference voltages. A set of switches are arranged and controlled to perform an algorithm for mitigating the influence of mismatches between the components. The switches are arranged between the reference voltage source and the resistive string so that switches in the reference inputs to the comparators are avoided. The resistive string is preferably circular. The converter can handle differential signals.

Claims (7)

1. A flash analog-to-digital converter for converting an analog input signal to a digital output code that is representative of the input signal, said analog-to-digital converter comprising a resistive string of substantially equal valued resistors and powered by a reference voltage source for providing a plurality of equidistant reference voltages, a set of comparators for comparing the analog input signal with said plurality of reference voltages, an encoder receiving the result of the set of comparators and deriving therefrom the digital output code and a switching circuit arranged and controlled to perform a mismatch mitigating algorithm, characterized in that the switching circuit is arranged between said reference voltage source and the resistive string to switch the reference voltage source at different clock cycles across different parts of the string in a systematic manner, wherein each of said parts comprises a fixed number of resistors.

2. A flash analog-to-digital converter for converting an analog input signal to a digital output code that is representative of the input signal, said analog-to-digital converter comprising a circular resistive string of substantially equal valued resistors and powered by a reference voltage source for providing a plurality of equidistant reference voltages, a set of comparators for comparing the analog input signal with said plurality of reference voltages, an encoder receiving the result of the set of comparators and deriving therefrom the digital output code and a switching circuit arranged and controlled to perform a mismatch mitigating algorithm, characterized in that the switching circuit is arranged between said reference voltage source and the resistive string to switch the reference voltage source at different clock cycles across different parts of the string, wherein each of said parts comprises a fixed number of resistors.

3. A flash analog-to-digital converter as claimed in claim 2 characterized in that at any clock cycle the reference voltage source is switched between two diagonally opposite tabs of the circular resistive string.

4. A flash analog-to-digital converter as claimed in claim 3 characterized in that the analog input signal is a differential signal, that one of the parts of the differential signal is compared with the reference voltages supplied by the taps of the half circular resistive string at one side of the connections of the reference voltage source and that the other part of the differential signal is compared with the reference voltages supplied by the taps of the half circular resistive string at the other side of the connections of the reference voltage source.

5. A flash analog-to-digital converter as claimed in claim 2 , wherein the reference voltage source is arranged to divide the string in two equal halves of n resistors, where n is greater than one.

6. A flash analog-to-digital converter for converting an analog input signal to a digital output code that is representative of the input signal, said analog-to-digital converter comprising a linear resistive string of substantially equal valued resistors and powered by a reference voltage source for providing a plurality of equidistant reference voltages, a set of comparators for comparing the analog input signal with said plurality of reference voltages, an encoder receiving the result of the set of comparators and deriving therefrom the digital output code and switching means arranged and controlled to perform a mismatch mitigating algorithm, characterized in that the switching means are arranged between said reference voltage source and the resistive string to switch the reference voltage source at different clock cycles across different parts of the string, in a systematic manner wherein each of said parts comprises a fixed number of resistors.

7. A flash analog-to-digital converter for converting an analog input signal to a digital output code that is representative of the input signal, said analog-to-digital converter comprising a resistive string of substantially equal valued resistors and powered by a reference voltage source for providing a plurality of equidistant reference voltages, a set of comparators for comparing the analog input signal with said plurality of reference voltages, an encoder receiving the result of the set of comparators and deriving therefrom the digital output code and switching means arranged and controlled to perform a mismatch mitigating algorithm, characterized in that the switching means are arranged between said reference voltage source and the resistive string to switch the reference voltage source at different clock cycles across different parts of the string, in a non-arbitrary manner wherein each of said parts comprises a fixed number of resistors.

Assignments (13)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
PATENT RELEASE Recorded Aug 17, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 039707/0471 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2011
From: NXP B.V.
To: ELIPOSKI REMOTE LTD., L.L.C.
Reel/Frame 026260/0637 →
CONFIRMATORY ASSIGNMENT Recorded Mar 1, 2011
From: PELGROM, MARCEL; KATOCH, ATUL; VERTREGT, MAARTEN
To: NXP B.V.
Reel/Frame 025864/0083 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 11, 2008
From: PELGROM, MARCEL; KATOCH, ATUL; VERTREGT, MAARTEN
To: NXP B.V.
Reel/Frame 021082/0683 →