IP Library Granted Patent US 8,234,103
Granted Patent B2
US 8,234,103 · App. 12/098,348 · Granted Jul 31, 2012

Physical realizations of a universal adiabatic quantum computer

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Quick Facts
Patent No.
US 8,234,103
App. No.
12/098,348
Granted
Jul 31, 2012
Kind
B2
Abstract

Devices, methods and articles advantageously allow communications between qubits to provide an architecture for universal adiabatic quantum computation. The architecture includes a first coupled basis A 1 B 1 and a second coupled basis A 2 B 2 that does not commute with the first basis A 1 B 1 .

Claims (22)

1. A quantum processor comprising:

a first set of qubits;

a second set of qubits;

a first set of coupling devices that are selectively operable to couple information between a first basis A 1 in a first qubit in the first set of qubits and a first basis B 1 in a second qubit in the first set of qubits thereby defining a first coupled basis A 1 B 1 ; and

a second set of coupling devices that are selectively operable to couple information between a second basis A 2 in a first qubit in the second set of qubits and a second basis B 2 in a second qubit in the second set of qubits thereby defining a second coupled basis A 2 B 2 , wherein at least one qubit in the first set of qubits is communicably coupled with at least one qubit in the second set of qubits, and wherein the first coupled basis A 1 B 1 and the second coupled basis A 2 B 2 do not commute.

2. The quantum processor of claim 1 wherein the first coupled basis A 1 B 1 is a basis XX and the second coupled basis A 2 B 2 is a basis ZZ.

3. The quantum processor of claim 1 wherein the first coupled basis A 1 B 1 is a basis ZX and the second coupled basis A 2 B 2 is a basis XZ.

4. The quantum processor of claim 1 wherein at least one qubit is simultaneously included in both the first and second sets of qubits.

5. The quantum processor of claim 1 further comprising:

a defined readout basis wherein at least one of the bases A 1 , B 1 , A 2 , and B 2 is in a same basis as the readout basis.

6. The quantum processor of claim 1 wherein at least one of the qubits of the first set of qubits is an effective qubit comprised of a plurality of individual qubits and individual couplers that couple the individual qubits to function effectively as a single qubit.

7. A quantum processor comprising:

a plurality of qubits;

a first programming interface that is communicably coupled to a Z-degree of freedom of at least one of the qubits;

a second programming interface that is communicably coupled to an X-degree of freedom of at least one of the qubits;

a first set of coupling devices, wherein each of the coupling devices in the first set of coupling devices is configured to communicably couple information between the Z-degree of freedom of at least two of the qubits; and

a second set of coupling devices, wherein each of the coupling devices in the second set of coupling devices is configured to communicably couple information between the X-degree of freedom of at least two of the qubits.

8. The quantum processor of claim 7 wherein the plurality of qubits includes a number of superconducting qubits.

9. The quantum processor of claim 8 wherein each of the superconducting qubits includes a respective qubit loop formed by a closed superconducting current path and a respective compound Josephson junction that interrupts the qubit loop and is formed by a closed superconducting current path that is interrupted by at least two Josephson junctions, and wherein a first programming interface is communicably coupled to the qubit loop of at least one of the superconducting qubits and a second programming interface is communicably coupled to the compound Josephson junction of at least one of the superconducting qubits.

10. The quantum processor of claim 9 wherein each of the coupling devices in the first set of coupling devices is configured to couple magnetic flux signals between the qubit loops of a respective pair of the superconducting qubits.

11. The quantum processor of claim 9 wherein each of the coupling devices in the second set of coupling devices is configured to couple charge signals between a respective pair of the superconducting qubits.

12. The quantum processor of claim 7 wherein at least one of the qubits of the first set of qubits is an effective qubit comprised of a plurality of individual qubits and individual couplers that couple the individual qubits to function effectively as a single qubit.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2025
From: PSPIB UNITAS INVESTMENTS II INC.
To: D-WAVE SYSTEMS INC.; 1372934 B.C. LTD.
Reel/Frame 070470/0098 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Apr 14, 2023
From: D-WAVE SYSTEMS INC.; 1372934 B.C. LTD.
To: PSPIB UNITAS INVESTMENTS II INC., AS COLLATERAL AGENT
Reel/Frame 063340/0888 →
RELEASE OF SECURITY INTEREST Recorded Sep 20, 2022
From: PSPIB UNITAS INVESTMENTS II INC., IN ITS CAPACITY AS COLLATERAL AGENT
To: D-WAVE SYSTEMS INC.
Reel/Frame 061493/0694 →
SECURITY INTEREST Recorded Mar 3, 2022
From: D-WAVE SYSTEMS INC.
To: PSPIB UNITAS INVESTMENTS II INC.
Reel/Frame 059317/0871 →
SECURITY INTEREST Recorded Nov 29, 2019
From: D-WAVE SYSTEMS INC.
To: BDC CAPITAL INC.
Reel/Frame 051144/0499 →
SECURITY INTEREST Recorded Mar 22, 2019
From: D-WAVE SYSTEMS INC.
To: BDC CAPITAL INC.
Reel/Frame 048674/0188 →
RELEASE OF SECURITY INTEREST Recorded Apr 13, 2017
From: VENTURE LENDING & LEASING VI, INC.; VENTURE LENDING & LEASING VII, INC.
To: D-WAVE SYSTEMS INC.
Reel/Frame 042252/0256 →
CORRECTIVE ASSIGNMENT TO REMOVE APPL. NO. 8733763 PREVIOUSLY RECORDED AT REEL: 034841 FRAME: 0497. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT. Recorded Jan 30, 2015
From: D-WAVE SYSTEMS INC.
To: VENTURE LENDING & LEASING VI, INC.; VENTURE LENDING & LEASING VII, INC.
Reel/Frame 034862/0237 →
SECURITY INTEREST Recorded Jan 29, 2015
From: D-WAVE SYSTEMS INC.
To: VENTURE LENDING & LEASING VI, INC.; VENTURE LENDING & LEASING VII, INC.
Reel/Frame 034841/0497 →