Video multiviewer system using direct memory access (DMA) registers and block RAM
A video multiviewer system includes a Graphics Processing Unit (GPU) that includes a GPU memory. A video input module is operative with the GPU for receiving video data and transferring the video data to the GPU memory via a Direct Memory Access (DMA). A programmable circuit such as a Field Programmable Gate Array (FPGA) includes a multi-ported and in one aspect a dual ported block Random Access Memory (RAM) configured for a plurality of DMA channels for receiving video data and allowing uninterrupted operation of consecutive DMA transfers of video data to the GPU memory. A display displays the multiple video windows based upon video data received within the GPU memory.
1. A video multiviewer system comprising:
a graphics processing unit (GPU) comprising a GPU memory;
a Direct Memory Access (DMA) controller;
a video input module configured to receive simultaneously a plurality of video streams corresponding to video data and transfer the video data to the GPU memory via DMA, wherein the video input module comprises a programmable circuit having dual-ported Block Random Access Memory (RAM) comprising first and second ports, wherein the first port is operative with a host and the second port is operative with the DMA controller, wherein the dual-ported Block RAM is configured with a plurality of DMA channels for receiving the video data based on a number of plurality of video streams received at the video input module and is further configured to allow uninterrupted operation of consecutive DMA transfers of the video data to the GPU memory, wherein the first port is configured to allow independent read/write access by the host for configuration of the plurality of DMA channels using the first port, and the second port is configured to access video data in the plurality of DMA channels using simultaneous read/write access by DMA controller through the second port; and
a display configured to receive the video data stored at the GPU memory and simultaneously present multiple video streams in respective windows of the display.
2. The video multiviewer system according to claim 1 , and further comprising a Read/Write controller and plurality of registers, wherein as the DMA controller operates on DMA channel “n,” the Read/Write controller is operative for pre-reading registers for DMA channel “n+1”.
3. The video multiviewer system according to claim 2 , wherein the DMA controller changes state variables in registers when the video data is transferred within DMA channel “n”.
4. The video multiviewer system according to claim 2 , wherein the DMA controller is operative for modifying the video data within registers and passing the video data back to the Read/Write controller to be stored back within the dual-ported Block RAM.
5. The video multiviewer system according to claim 1 , and further comprising a video data controller operative with the video input module for assigning addresses to be used for the video data within the GPU memory.
6. The video multiviewer system according to claim 1 , and further comprising a plurality of video scalers operating in parallel for generating initially scaled video data by performing video scaling in at least one dimension on the plurality of video streams.
7. A video multiviewer system comprising:
a graphics processing unit (GPU) comprising a GPU memory;
a Direct Memory Access (DMA) controller;
a Read/Write controller;
a video input module configured to receive simultaneously a plurality of video streams corresponding to video data and transfer the video data to the GPU memory via DMA, wherein the video input module comprises a Field Programmable Gate Array (FPGA) comprising a dual ported Block Random Access Memory (RAM) comprising Pre-read registers, Write Back registers and Working registers, and further comprising first and second ports, wherein the dual-ported Block RAM is configured with a plurality of DMA channels for receiving the video data based on a number of plurality of video streams received at the video input module, wherein the first port is operative with a host and the second port is operative with the DMA controller, wherein the DMA controller and the Read/Write controller are operative together with the Pre-read registers, Write Back registers and Working registers for receiving the video data and allowing uninterrupted operation of consecutive DMA transfers of the video data to the GPU memory, wherein the first port is configured to allow independent read/write access by the host for configuration of the plurality of DMA channels through the first port, and the second port is configured to access the video data of the plurality of DMA channels using simultaneous read/write access by the DMA controller through the second port; and
a display configured to receive the video data stored at the GPU memory and simultaneously present video streams in respective windows of the display.
8. The video multiviewer system according to claim 7 , wherein as the DMA controller operates on DMA channel “n,” the Read/Write controller is operative for pre-reading registers for DMA channel “n+1.
9. The video multiviewer system according to claim 7 , wherein the DMA controller changes state variables in registers when the video data is transferred within DMA channel “n”.
10. The video multiviewer system according to claim 7 , wherein the DMA controller is operative for modifying the video data and passing the video data back to the Read/Write controller to be stored back the dual-ported Block RAM.
11. The video multiviewer system according to claim 7 , and further comprising a video data controller operative with the video input module for assigning addresses to be used for the video data within the GPU memory.
12. The video multiviewer system according to claim 7 , and further comprising a plurality of video scalers operating in parallel for generating initially scaled video data by performing video scaling in at least one dimension on the plurality of video streams.
13. A method for displaying multiple video windows on a video multiviewer display, comprising:
receiving, at a video input module, simultaneously a plurality of video streams corresponding to video data, wherein the video input module is coupled to a Graphics Processing Unit (GPU) having a GPU memory and further coupled to a DMA controller;
transferring the video data to the GPU memory via DMA through a programmable circuit having a dual ported Block Random Access Memory (RAM) comprising first and second ports, wherein the first port is operative with a host and the second port is operative with the DMA controller, wherein the dual-ported Block RAM is configured with a plurality of DMA channels for receiving the video data based on a number of plurality of video streams received at the video input module and is further configured to allow uninterrupted operation of consecutive DMA transfers of the video data to the GPU memory, wherein the first port is configured to allow independent read/write access by the host for configuration of the plurality of DMA channels through the first port, and the second port is configured to access video data in the plurality of DMA channels using simultaneous read/write access by the DMA controller through the second port;
receiving, at a display, the video data stored at the GPU memory; and
presenting simultaneously video streams in respective windows.
14. The method according to claim 13 , which further comprises operating on DMA channel “n” with the DMA controller while the Read/Write controller pre-reads registers for DMA channel “n+1”.
15. The method according to claim 13 , which further comprises changing state variables in registers while transferring the video data within DMA channel “n”.
16. The method according to claim 13 , which further comprises modifying the video data within registers and passing the video data back to the Read/Write controller to be stored back within the dual-ported Block RAM.
17. The method according to claim 13 , which further comprises assigning addresses for the video data within the GPU memory.
18. The method according to claim 13 , which further comprises scaling the video data within a plurality of video scalers operating in parallel and generating initially scaled video data by performing video scaling in at least one dimension on the plurality of video streams.