Processor emulation using speculative forward translation

1. A method for emulating a target system on a host system having one or more processors, the method comprising:

a) identifying one or more potential candidates for forward translation from one or more portions of target system code;

b) assigning a priority for forward translation to each of the one or more potential candidates;

c) determining whether any of the one or more potential candidates is a valid candidate for forward translation; and

d) discarding any potential candidates determined to be invalid before beginning translation, and translating any potential candidates determined to be valid with the host system to produce one or more corresponding blocks of translated code executable by the host system,

wherein determining whether any of the one or more potential candidates is a valid candidate for forward translation includes discarding a candidate that is located outside a valid memory area for the target code.

2. The method of claim 1 wherein c) comprises discarding a target of a function call if it doesn't meet an expected structure of a typical function.

3. The method of claim 1 wherein c) comprises discarding a potential candidates containing an illegal instruction.

4. The method of claim 1 wherein d) includes stopping translation if an invalid instruction is encountered.

5. The method of claim 1 , wherein c) includes determining whether a potential candidate contains little or no useful instructions and discarding the potential candidate if it contains little or no useful instructions.

6. The method of claim 1 , further comprising storing the translated code in a cache.

7. The method of claim 6 , further comprising periodically removing stale entries from the cache.

8. The method of claim 6 , further comprising deleting entries from a defragmentation pointer onwards until sufficient space is available in the cache for a block of translated code that would not otherwise fit in the cache.

9. The method of claim 1 , further comprising validating the translated code by determining whether the corresponding target system code has been changed since it was translated.

10. The method of claim 1 , further comprising executing the translated code with the host system.

11. The method of claim 1 , wherein a) comprises determining if an area of memory corresponding to a translation request contains a memory address that is about to be executed and analyzing a memory area of code corresponding to the translation request to identify potential translation targets.

12. The method of claim 11 wherein, if the memory area contains function calls or jumps to other target code that has not yet been translated, a) further comprises identifying such function calls or target code as potential candidates for speculative translation.

13. The method of claim 1 , wherein a) comprises identifying an area of memory as containing a potential candidate for forward translation based on the presence in that area of a function that has a stack that is incremented or decremented and has a return instruction.

14. The method of claim 1 , wherein b) comprises assigning the priority based on a likelihood of imminent execution of the potential candidate.

15. An apparatus for emulating a target system on a host system having one or more processors, comprising:

a processor module coupled to a memory;

a speculative forward translation thread containing processor executable instructions adapted to be executed by the processor module, wherein the speculative forward translation thread includes:

a) an instruction that, when executed, identifies one or more potential candidates for forward translation from one or more portions of target system code;

b) an instruction that, when executed, assigns a priority for forward translation to each of the one or more potential candidates;

c) an instruction that, when executed, determines whether any of the one or more potential candidates is a valid candidate for forward translation, wherein determining whether any of the one or more potential candidates is a valid candidate for forward translation includes discarding a candidate that is located outside a valid memory area for the target code; and

d) an instruction that, when executed, discards any potential candidates determined to be invalid before beginning translation, and translates any potential candidates determined to be valid to produce one or more corresponding blocks of translated code executable by the host system.

16. The apparatus of claim 15 wherein the processor module includes a single core processor.

17. The apparatus of claim 15 wherein the processor module includes a multi core processor.

18. The apparatus of claim 15 wherein the processor module includes a cell processor.

19. The apparatus of claim 15 , wherein the memory includes a cache and wherein the speculative forward translation thread includes an instruction that, when executed, stores the blocks of translated code in the cache.

20. The apparatus of claim 19 , further comprising a watchdog thread adapted to be executed by the processor module, wherein the watchdog thread includes one or more instructions that, when executed periodically remove stale translated code entries from the cache.

21. The apparatus of claim 19 , further comprising one or more instructions that, when executed, delete entries in the cache from a defragmentation pointer onwards until sufficient space is available in the cache for a block of translated code that would not otherwise fit in the cache.

22. The apparatus of claim 19 wherein the cache is configured as a heap structure that is doubly linked.

23. The apparatus of claim 15 , further comprising one or more instructions that, when executed, validate one or more of the blocks of translated code prior to their execution.

24. The apparatus of claim 15 , further comprising one or more instructions that, when executed, cause one or more of the blocks of translated code to be executed by the processor module.