Thin film transistor array panel and fabrication
View Patent ↗The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.
1. A thin film transistor array panel comprising:
a substrate;
a gate line formed on the substrate;
a gate insulating layer formed on the substrate;
a semiconductor layer formed on the substrate;
a data line formed on the semiconductor layer and having a source electrode;
a drain electrode formed on the semiconductor layer and disposed opposite the source electrode; and
a pixel electrode connected to the drain electrode,
wherein the data line includes a first conducting film including Mo, a second conducting film including Al formed on the first conducting film, and a third film including Mo formed on the second conducting film,
wherein the semiconductor layer includes a first portion having substantially the same planar shape as the data line and the drain electrode and a second portion disposed and exposing between the source electrode and the drain electrode, and
wherein the second portion includes Cl atoms of 3.0 to 20 at %.
2. The thin film transistor array panel of claim 1 , further comprising an ohmic contact formed between the semiconductor layer and the data line.
3. The thin film transistor array panel of claim 1 , wherein the gate line includes a conducting film including Al and a conducting film including Mo.
4. The thin film transistor array panel of claim 3 , wherein the conducting film including a conducting film including Al made of AlNd.
5. The thin film transistor array panel of claim 1 , wherein the first and the third conducting film including Mo is one selected from Mo, MoN, MoNb, MoV, MoTi, and MoW.
6. The thin film transistor array panel of claim 1 , wherein the second conducting film includes AlNd.