Delta-sigma AD converter apparatus using delta-sigma modulator circuit provided with reset circuit resetting integrator
View Patent ↗In a delta-sigma modulator circuit, an integrator integrates an input signal, and a quantization circuit quantizes the integrated signal with a predetermined quantization number, and outputs a quantization result signal. A DA converter circuit outputs an analog signal indicating a DA conversion result based on the quantization result signal. An oscillation detector circuit detects that the integrator is in an oscillation state based on the integrated signal, and outputting an oscillation detection signal. A reset circuit resets the integrator based on the oscillation detection signal.
1. A delta-sigma modulator circuit comprising:
an integrator for integrating an input signal;
a quantization circuit for quantizing the integrated signal with a predetermined quantization number, and outputting a quantization result signal; and
a DA converter circuit for outputting an analog signal indicating a DA conversion result based on the quantization result signal,
wherein the quantization circuit further comprises an oscillation detector circuit for detecting that the integrator is in an oscillation state based on the integrated signal, and outputting an oscillation detection signal, and
wherein the delta-sigma modulator circuit further comprises a reset circuit for resetting the integrator based on the oscillation detection signal.
2. The delta-sigma modulator circuit as claimed in claim 1 ,
wherein the quantization circuit includes a plurality of quantizers corresponding to the predetermined quantization number,
wherein the oscillation detector circuit includes:
an excessively high input detection quantizer for detecting that the integrated signal is equal to or higher than a first threshold value that is an excessively high input threshold value, and outputting an excessively high input detection signal;
an excessively low input detection quantizer for detecting that the integrated signal is lower than a second threshold value that is an excessively low input threshold value, and outputting an excessively low input detection signal; and
a signal generator circuit for generating the oscillation detection signal based on the excessively high input detection signal and the excessively low input detection signal.
3. The delta-sigma modulator circuit as claimed in claim 1 ,
wherein the reset circuit discharges electric charges accumulated in an integral capacitor included in the integrator.
4. The delta-sigma modulator circuit as claimed in claim 2 ,
wherein the reset circuit discharges electric charges accumulated in an integral capacitor included in the integrator.
5. The delta-sigma modulator circuit as claimed in claim 1 , further comprising:
an operational amplifier included in the integrator which is turned into a sleep state based on the oscillation detection signal.
6. The delta-sigma modulator circuit as claimed in claim 2 , further comprising:
an operational amplifier included in the integrator which is turned into a sleep state based on the oscillation detection signal.
7. The delta-sigma modulator circuit as claimed in claim 1 , further comprising:
a sampling capacitor included in the integrator, wherein electric charges accumulated in the sampling capacitor are discharged based on the oscillation detection signal.
8. The delta-sigma modulator circuit as claimed in claim 2 , further comprising:
a sampling capacitor included in the integrator, wherein electric charges accumulated in the sampling capacitor are discharged based on the oscillation detection signal.
9. The delta-sigma modulator circuit as claimed in claim 1 , further comprising:
a sampling capacitor included in the DA converter circuit, wherein electric charges accumulated in the sampling capacitor are discharged based on the oscillation detection signal.
10. The delta-sigma modulator circuit as claimed in claim 1 , further comprising:
a sampling capacitor included in the DA converter circuit, wherein electric charges accumulated in the sampling capacitor are discharged based on the oscillation detection signal.
11. A delta-sigma AD converter apparatus for performing a delta-sigma AD conversion on an input signal, the delta-sigma AD converter apparatus comprising a delta-sigma modulator circuit,
wherein a delta-sigma modulator circuit comprises:
an integrator for integrating an input signal;
a quantization circuit for quantizing the integrated signal with a predetermined quantization number, and outputting a quantization result signal; and
a DA converter circuit for outputting an analog signal indicating a DA conversion result based on the quantization result signal,
wherein the quantization circuit further comprises an oscillation detector circuit for detecting that the integrator is in an oscillation state based on the integrated signal, and outputting an oscillation detection signal, and
wherein the delta-sigma modulator circuit further comprises a reset circuit for resetting the integrator based on the oscillation detection signal.
12. The delta-sigma AD converter apparatus as claimed in claim 11 ,
wherein the quantization circuit includes a plurality of quantizers corresponding to the predetermined quantization number,
wherein the oscillation detector circuit includes:
an excessively high input detection quantizer for detecting that the integrated signal is equal to or higher than a first threshold value that is an excessively high input threshold value, and outputting an excessively high input detection signal;
an excessively low input detection quantizer for detecting that the integrated signal is lower than a second threshold value that is an excessively low input threshold value, and outputting an excessively low input detection signal; and
a signal generator circuit for generating the oscillation detection signal based on the excessively high input detection signal and the excessively low input detection signal.