Semiconductor integrated circuit

1. A semiconductor integrated circuit comprising:

a plurality of memory cells arranged in a matrix;

a plurality of word lines corresponding to respective rows of the plurality of memory cells;

a plurality of word line drivers for driving the plurality of word lines, respectively; and

a plurality of pull-down circuits connected to the plurality of word lines, respectively, for causing voltages of the respective connected word lines to be lower than or equal to a power supply voltage when the respective word lines are in an active state,

wherein the plurality of word line drivers each has a PMOS transistor for causing the corresponding word line to go into the active state, and

the plurality of pull-down circuits each has a PMOS pull-down transistor for pulling down a voltage of the corresponding word line.

2. The semiconductor integrated circuit of claim 1 , wherein the PMOS pull-down transistor is controlled in accordance with a word line voltage adjustment signal given to a gate terminal thereof.

3. The semiconductor integrated circuit of claim 2 , wherein the plurality of pull-down circuits each includes a plurality of the PMOS pull-down transistors, and

different word line voltage adjustment signals are input separately to the gate terminals of the plurality of PMOS pull-down transistors possessed by each of the plurality of pull-down circuits.

4. The semiconductor integrated circuit of claim 2 , wherein the PMOS pull-down transistor is caused to go into a non-conductive state in accordance with the word line voltage adjustment signal.

5. The semiconductor integrated circuit of claim 2 , further comprising:

a pull-down control circuit having a plurality of transistors having the same conductivity type connected in series, for outputting the word line voltage adjustment signal from a node between each of the transistors connected in series.

6. The semiconductor integrated circuit of claim 5 , wherein the pull-down control circuit outputs the word line voltage adjustment signal for causing the PMOS pull-down transistor to be conductive when any of the plurality of word lines is in the active state.

7. The semiconductor integrated circuit of claim 2 , further comprising:

a transistor characteristics measuring circuit having a measuring transistor on the same semiconductor substrate on which the semiconductor integrated circuit is provided.

8. The semiconductor integrated circuit of claim 7 , wherein

the measuring transistor is a transistor having a configuration similar to that of the transistors included in the plurality of memory cells.

9. The semiconductor integrated circuit of claim 8 , wherein

the transistor characteristics measuring circuit has a plurality of the measuring transistor, and the plurality of measuring transistors are connected in parallel.

10. The semiconductor integrated circuit of claim 7 , further comprising:

an additional transistor characteristics measuring circuit the same as the transistor characteristics measuring circuit,

wherein the transistor characteristics measuring circuits correspond to respective transistor groups each having a plurality of transistors included in the semiconductor integrated circuit, and

the transistors included in each transistor group have a threshold voltage different from that of the transistors included in the other transistor group.

11. The semiconductor integrated circuit of claim 1 , wherein

the word line driver causes a period of time during which any of the plurality of word lines is in the active state to have a length corresponding to the number of bits which can be stored in the plurality of memory cells.

12. The semiconductor integrated circuit of claim 1 , wherein

the plurality of pull-down circuits causes drive capability thereof to have a level corresponding to the number of bits which can be stored in the plurality of memory cells.