Identification of board connections for differential receivers
View Patent ↗Embodiments of the invention include testing arrangements for detecting proper DC-coupled board connections on the input legs of a differential receiver. The testing implementation includes a first test receiver AC-coupled to the connection between the first input/output (I/O) pad and the differential receiver positive input and/or a second test receiver coupled to the connection between the second I/O pad and the differential receiver negative input. The test receiver protects the test receiver input from DC voltages applied to the differential receiver via the differential receiver input. Also, the test receiver includes a high-pass filter arrangement that generates data capable of detecting whether the I/O pad connected to the test receiver has a proper DC-coupled connection or an improper connection when presented with a stimulus pulse. The test receiver is less susceptible to noise because than conventional arrangements that use a low-pass RC filter.
1. A device for testing the connections to a differential receiver, wherein the differential receiver includes a first positive input connected to a first input/output pad, a second negative input connected to a second input/output pad, and an output, comprising:
at least one test receiver coupled to a corresponding one of the first input/output pad and the second input/output pad, wherein the test receiver includes a single-ended comparator with an output coupled to an input of a data storage register, and wherein the test receiver includes an output coupled to a JTAG capture register, wherein at least one capture/update register is coupled to the output of the differential receiver, and wherein the JTAG capture register is coupled to the capture/update register; and
a capacitor coupled in series between the input/output pad and the input to the test receiver in a manner that protects the input of the test receiver from DC voltages coupled to the differential receiver via the input of the differential receiver, and
wherein the at least one test receiver includes a high-pass filter arrangement that generates data of a first type if the input/output pad coupled to the test receiver has a proper DC-coupled connection and data of a second type if the input/output pad coupled to the test receiver has an improper connection.
2. The device as recited in claim 1 , wherein, if the input/output pad has a DC voltage coupled thereto, the test receiver is configured to generate the first type of data if the DC voltage is within a first voltage level operating range for the differential receiver and configured to generate the second type of data if the DC voltage is not within the first voltage level operating range for the differential receiver.
3. The device as recited in claim 1 , wherein the test receiver is configured to generate the second type of data if the corresponding input/output pad has an open connection.
4. The device as recited in claim 1 , wherein the differential receiver is part of a boundary scan architecture.
5. A differential input circuit, comprising:
a differential receiver having a first positive input, a second negative input and an output;
a first input/output pad coupled to the first positive input;
a second input/output pad coupled to the second negative input;
a first test receiver having a first test receiver input;
a second test receiver having a second test receiver input;
a first capacitor coupled in series between the first input/output pad and the first test receiver input, wherein the first test receiver is AC-coupled to the first input/output pad in a manner that protects the first test receiver input from DC voltages coupled thereto; and
a second capacitor coupled in series between the second input/output pad and the second test receiver input, wherein the second test receiver is AC-coupled to the second input/output pad in a manner that protects the second test receiver input from DC voltages coupled thereto,
wherein the first and second test receivers each include a single-ended comparator with an input coupled in series to the corresponding capacitor and a data storage register with an input coupled in series to the output of the single-ended comparator, and wherein the first and second test receivers each include an output coupled to a JTAG capture register, wherein at least one JTAG capture/update register is coupled to the output of the differential receiver, and wherein the JTAG capture registers are coupled to the JTAG capture/update register, and
wherein each of the first and second test receivers includes a high-pass filter arrangement that generates data of a first type if the input/output pad coupled thereto has a proper DC-coupled connection and data of a second type if the input/output pad coupled thereto has an improper connection.
6. The differential input circuit as recited in claim 5 , wherein at least one of the first and second test receivers is configured to determine if a DC voltage coupled to the corresponding input/output pad has a voltage level that is within a proper voltage level operating range for the differential input circuit.
7. The differential input circuit as recited in claim 5 , wherein, if at least one of the input/output pads has a DC voltage coupled thereto, the corresponding test receiver coupled thereto is configured to generate the first type of data if the DC voltage is within a first voltage level operating range for the differential receiver and configured to generate the second type of data if the DC voltage is not within the first voltage level operating range for the differential receiver.
8. The differential input circuit as recited in claim 5 , wherein the at least one test receiver is configured to generate the second type of data if the corresponding input/output pad has an open connection.
9. The differential input circuit as recited in claim 5 , wherein at least one of the first and second test receivers is configured to determine if the corresponding input/output pad connected thereto has an open connection or is DC coupled.
10. The differential input circuit as recited in claim 5 , wherein the differential input circuit is part of a boundary scan testing circuitry arrangement.
11. The differential input circuit as recited in claim 5 , wherein the first test receiver includes an input coupled between the first input/output pad and the first positive input, and wherein the second test receiver includes an input coupled between the second input/output pad and the second negative input, and wherein the JTAG capture registers and the JTAG capture/update register are part of a boundary scan architecture.