SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT METHOD FOR THE SAME

1 . A semiconductor integrated circuit comprising a clock distribution circuit for distributing a clock signal in a functional block constructed by using standard cells, the clock distribution circuit including:

a first clock main line extending along a first direction;

a first clock branch line group including a plurality of clock branch lines extending along a second direction perpendicular to the first direction and electrically connected to the first clock main line;

a first clock driving cell electrically connected to the first clock main line;

a first clock synchronous cell group including a plurality of clock synchronous cells electrically connected to the first clock main line or the first clock branch line group;

a second clock main line extending in parallel to the first clock main line;

a second clock branch line group including a plurality of clock branch lines extending along the second direction and electrically connected to the second clock main line;

a second clock driving cell electrically connected to the second clock main line;

a second clock synchronous cell group including a plurality of clock synchronous cells electrically connected to the second clock main line or the second clock branch line group; and

a clock source driver for providing a clock signal to the first clock driving cell and the second clock driving cell,

the first clock branch line group being electrically separated from the second clock branch line group,

the first clock driving cell singly driving the first clock main line and the first clock branch line group,

the second clock driving cell singly driving the second clock main line and the second clock branch line group.

2 . The semiconductor integrated circuit of claim 1 ,

wherein the semiconductor integrated circuit includes a plurality of interconnection layers having a large thickness in an upper layer and a small thickness in a lower layer,

the first clock main line and the second clock main line are formed by using an interconnection of the upper layer with a large thickness,

each of the plurality of clock synchronous cells included in the first clock synchronous cell group is connected, by using an interconnection of the lower layer with a small thickness, to the first clock main line or the first clock branch line group placed in a position at a shortest distance along a forward or reverse direction of the first direction, and

each of the plurality of clock synchronous cells included in the second clock synchronous cell group is connected, by using an interconnection of the lower layer with a small thickness, to the second clock main line or the second clock branch line group placed in a position at a shortest distance along a forward or reverse direction of the first direction.

3 . The semiconductor integrated circuit of claim 1 ,

wherein a first region whose range along the first direction is defined by the first clock main line and whose range along the second direction is defined by the first clock branch line group and a second region whose range along the first direction is defined by the second clock main line and whose range along the second direction is defined by the second clock branch line group are exclusive from each other,

the first clock synchronous cell group is placed in the first region,

the second clock synchronous cell group is placed in the second region,

the first clock main line is placed at a center of the first region, and

the second clock main line is placed at a center of the second region.

4 . The semiconductor integrated circuit of claim 1 ,

wherein a line path for connecting the first clock driving cell to the first clock main line and a line path for connecting the second clock driving cell to the second clock main line are formed by using lines with a large width and a plurality of contacts.

5 . The semiconductor integrated circuit of claim 1 ,

wherein the plurality of clock branch lines included in the first clock branch line group are placed bilaterally symmetrically about the first clock main line at constant intervals along the first direction, and

the plurality of clock branch lines included in the second clock branch line group are placed bilaterally symmetrically about the second clock main line at constant intervals along the first direction.

6 . The semiconductor integrated circuit of claim 1 ,

wherein the number of the plurality of clock branch lines included in the first clock branch line group is different from the number of the plurality of clock branch lines included in the second clock branch line group.

7 . The semiconductor integrated circuit of claim 1 ,

wherein the first clock driving cell is placed at a center of the first clock main line,

the second clock driving cell is placed at a center of the second clock main line, and

the first clock driving cell and the second clock driving cell have different driving performance.

8 . The semiconductor integrated circuit of claim 1 ,

wherein the plurality of clock branch lines included in the first clock branch line group are placed bilaterally asymmetrically about the first clock main line, and

some of the plurality of clock branch lines included in the first clock branch line group have a different length.

9 . The semiconductor integrated circuit of claim 1 ,

wherein the plurality of clock branch lines included in the first clock branch line group are placed bilaterally asymmetrically about the first clock main line, and

some of the plurality of clock branch lines included in the first clock branch line group have a different length and a different width.

10 . The semiconductor integrated circuit of claim 1 ,

wherein the clock distribution circuit further includes:

a third clock main line extending along the first direction;

a third clock branch line group including a plurality of clock branch lines extending along the second direction and electrically connected to the third clock main line;

a third clock driving cell electrically connected to the third clock main line for driving merely the third clock main line and the third clock branch line group; and

a third clock synchronous cell group including a plurality of clock synchronous cells electrically connected to the third clock main line or the third clock branch line group,

the first clock main line, the second clock main line and the third clock main line are arranged in this order along the second direction,

a distance between the first clock main line and the second clock main line and a distance between the second clock main line and the third clock main line are different from each other, and

the first clock branch line group, the second clock branch line group and the third clock branch line group are different from one another in length of the clock branch lines included therein.

11 . The semiconductor integrated circuit of claim 1 ,

wherein the first clock main line and the second clock main line have different lengths.

12 . The semiconductor integrated circuit of claim 1 ,

wherein the clock distribution circuit further includes:

a third clock main line extending along the first direction on a side of the second clock main line along a forward or reverse direction of the first direction;

a third clock branch line group including a plurality of clock branch lines extending along the second direction and electrically connected to the third clock main line;

a third clock driving cell electrically connected to the third clock main line for driving merely the third clock main line and the third clock branch line group; and

a third clock synchronous cell group including a plurality of clock synchronous cells electrically connected to the third clock main line or the third clock branch line group, and

the first clock main line has a length larger than a sum of lengths of the second clock main line and the third clock main line.

13 . The semiconductor integrated circuit of claim 1 ,

wherein the clock distribution circuit further includes a hard macro placed at a center of the first clock main line or the second clock main line, and

the first clock driving cell and the second clock driving cell are placed so as not to overlap the hard macro and to be spaced from each other along the first direction.

14 . The semiconductor integrated circuit of claim 1 ,

wherein the clock distribution circuit further includes a hard macro having a plurality of clock connection pins each for receiving a clock signal,

the semiconductor integrated circuit includes a plurality of interconnection layers having a large thickness in an upper layer and a small thickness in a lower layer, and

each clock connection pin is connected, by using an interconnection of the lower layer with a small thickness, to one line placed in a position at a shortest distance along a forward or reverse direction of the first direction out of the plurality of clock branch lines included in the first clock branch line group, the plurality of clock branch lines included in the second clock branch line group, or the first clock main line and the second clock main line.

15 . The semiconductor integrated circuit of claim 1 ,

wherein the first clock driving cell and the second clock driving cell respectively have clock connection pins each for supplying a clock signal,

the clock connection pins are aligned straight, and

a portion from the clock source driver to the clock connection pins of the first clock driving cell and the second clock driving cell is constructed by using a buffer tree of a plurality of stages respectively having the same length.

16 . The semiconductor integrated circuit of claim 15 ,

wherein the clock distribution circuit further includes:

a third clock main line extending along the first direction on a side of the first clock main line along a forward or reverse direction of the first direction;

a third clock branch line group including a plurality of clock branch lines extending along the second direction and electrically connected to the third clock main line;

a third clock driving cell electrically connected to the third clock main line for driving merely the third clock main line and the third clock branch line group;

a third clock synchronous cell group including a plurality of clock synchronous cells electrically connected to the third clock main line or the third clock branch line group;

a fourth clock main line extending along the first direction on a side of the second clock main line along a forward or reverse direction of the first direction;

a fourth clock branch line group including a plurality of clock branch lines extending along the second direction and electrically connected to the fourth clock main line;

a fourth clock driving cell electrically connected to the fourth clock main line for driving merely the fourth clock main line and the fourth clock branch line group; and

a fourth clock synchronous cell group including a plurality of clock synchronous cells electrically connected to the fourth clock main line or the fourth clock branch line group,

the third clock driving cell and the forth clock driving cell respectively have clock connection pins each for supplying a clock signal, and

a portion from the clock source driver to the clock connection pins of the third clock driving cell and the fourth clock driving cell is constructed by using another buffer tree of a plurality of stages respectively having the same length.

17 . The semiconductor integrated circuit of claim 15 ,

wherein the clock distribution circuit further includes:

a third clock main line extending along the first direction on a side of the first clock main line along a forward or reverse direction of the first direction;

a third clock branch line group including a plurality of clock branch lines extending along the second direction and electrically connected to the third clock main line;

a third clock driving cell electrically connected to the third clock main line for driving merely the third clock main line and the third clock branch line group;

a third clock synchronous cell group including a plurality of clock synchronous cells electrically connected to the third clock main line or the third clock branch line group;

a fourth clock main line extending along the first direction on a side of the second clock main line along a forward or reverse direction of the first direction;

a fourth clock branch line group including a plurality of clock branch lines extending along the second direction and electrically connected to the fourth clock main line;

a fourth clock driving cell electrically connected to the fourth clock main line for driving merely the fourth clock main line and the fourth clock branch line group; and

a fourth clock synchronous cell group including a plurality of clock synchronous cells electrically connected to the fourth clock main line or the fourth clock branch line group,

the third clock driving cell and the fourth clock driving cell respectively have clock connection pins each for supplying a clock signal, and

the buffer tree is shared by a portion from the clock source driver to the clock connection pins of the third clock driving cell and the fourth clock driving cell.

18 . The semiconductor integrated circuit of claim 1 ,

wherein the clock distribution circuit further includes:

a third clock main line extending along the first direction;

a third clock branch line group including a plurality of clock branch lines extending along the second direction and electrically connected to the third clock main line;

a third clock driving cell electrically connected to the third clock main line for driving merely the third clock main line and the third clock branch line group;

a third clock synchronous cell group including a plurality of clock synchronous cells electrically connected to the third clock main line or the third clock branch line group;

a fourth clock main line extending along the first direction;

a fourth clock branch line group including a plurality of clock branch lines extending along the second direction and electrically connected to the fourth clock main line;

a fourth clock driving cell electrically connected to the fourth clock main line for driving merely the fourth clock main line and the fourth clock branch line group;

a fourth clock synchronous cell group including a plurality of clock synchronous cells electrically connected to the fourth clock main line or the fourth clock branch line group; and

another clock source driver for providing a clock signal to the third clock driving cell and the fourth clock driving cell,

the first clock main line, the second clock main line, the third clock main line and the fourth clock main line are arranged in this order along the second direction, and

different clock signals are respectively input to the clock source driver for providing a clock signal to the first clock driving cell and the second clock driving cell and the clock source driver for providing a clock signal to the third clock driving cell and the fourth clock driving cell.

19 . A layout method for a semiconductor integrated circuit including a clock distribution circuit for distributing a clock signal, comprising:

a region dividing step of dividing a functional block including the clock distribution circuit into a plurality of regions along a first direction;

a main line placement step of providing a clock main line at a center of each region to extend along the first direction by using an interconnection of an upper layer with a large thickness;

a branch line placement step of providing a plurality of clock branch lines to extend along a second direction perpendicular to the first direction with the clock main line set as a center;

a driving cell placement/connection step of providing a clock driving cell for driving the clock main line and the clock branch lines at the center of each region and forming a line for connecting the clock driving cell to the clock main line;

a clock connection step of forming a line for connecting each clock synchronous cell placed in each region to one of the clock main line and the clock branch lines placed nearby in the same region; and

a buffer tree building step of building a buffer tree extending from a clock source driver to the clock driving cell.