IP Library Patent Application 12102700
Patent Application
App. No. 12/102,700

CARBON NANOTUBE MEMORY CELLS HAVING FLAT BOTTOM ELECTRODE CONTACT SURFACE

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Patent No.
US None
App. No.
12/102,700
Abstract

The present invention is directed to structures and methods of fabricating nanotube electromechanical memory cells having a bottom electrode with a substantially planar contact surface. The bottom electrode is configured so that during the operation of the memory cell the nanotube crossbar of the cell can make contact with a substantially planar surface of the bottom electrode.

Claims (28)

1 . A nanotube electromechanical memory apparatus comprising:

a semiconductor substrate having a nanotube electromechanical memory cell formed thereon, the memory cell including a transistor with a bottom electrode comprising a substantially planar contact surface enabling a nanotube crossbar of the memory cell to contact the substantially planar contact surface of the bottom electrode during operation of the memory cells,

wherein the bottom electrode comprises a copper filled via enabling electrical contact with the transistor and having a substantially planar top surface comprising the substantially planar contact surface of the bottom electrode.

2 . The apparatus of claim 1 comprising a copper barrier layer between the copper filled via and the bottom electrode.

3 . The apparatus of claim 2 , wherein the barrier layer is about 100 angstroms to about 1500 angstroms thick.

4 . The apparatus of claim 2 , wherein the barrier layer is selected from the group consisting of tantalum, titanium, titanium nitride, tantalum nitride, titanium silicon nitride, and tungsten nitride.

5 . The apparatus of claim 2 , wherein the barrier layer comprises a bilayer. 6 . The apparatus 5 , wherein the bilayer comprises at least one or Ti/TiN or Ti/TaN.

7 . The apparatus of claim 2 comprising a copper seed layer between the barrier layer and the copper filled via.

8 . The apparatus of claim 7 , wherein the copper seed layer is between about 100 angstroms and about 2500 angstroms thick.

9 . A method of a forming a bottom electrode contact surface in a nanotube electromechanical memory cell, the method comprising:

providing a semiconductor substrate having an opening formed therein, the opening configured to enable electrical contact with an underlying transistor of an electromechanical memory cell; and

forming a bottom electrode that extends into the opening enabling electrical connection with the transistor such that the bottom electrode has a substantially planar top contact surface enabling a nanotube crossbar of the memory cell to contact the top contact surface of the bottom electrode during operation of the memory cell,

wherein forming the bottom electrode comprises:

filling the opening with copper; and

planarizing the surface to form a substantially planar top contact surface.

10 . The method of forming a bottom electrode contact surface in a nanotube electromechanical memory cell as in claim 9 , wherein filling the opening with copper comprises:

forming a barrier layer on the substrate;

forming a conductive seed layer on the barrier;

plating the seed layer with copper to form a bulk copper that fills the opening; and

wherein planarizing the surface comprises chemical mechanical polishing of the surface to planarize the bulk copper layer in the opening to form a conductive via having a substantially planarized top surface enabling the nanotube crossbar of the memory cell to contact the substantially planarized top surface of the bottom electrode during operation of the memory cell.

11 . The method of claim 10 , wherein forming a conductive seed layer comprises physical vapor deposition.

12 . The method of claim 10 , wherein plating the seed layer with copper comprises electrochemical plating.

13 . The method of claim 10 , wherein the barrier layer is about 100 angstroms to about 1500 angstroms thick.

14 . The method of claim 10 , wherein the barrier layer is selected from the group consisting of tantalum, titanium, titanium nitride, tantalum nitride, titanium silicon nitride, and tungsten nitride.

15 . The method of claim 10 , wherein the barrier layer comprises a bilayer.

16 . The method 10 , wherein the bilaver comprises at least one or Ti/TiN or Ti/TaN.

17 . The method of claim 10 , wherein the copper seed layer is between about 100 angstroms and about 2500 angstroms thick.

18 - 21 . (canceled)

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2008
From: LSI LOGIC CORPORATION
To: NANTERO, INC.
Reel/Frame 020930/0839 →