Using programming-time information to support error correction
View Patent ↗Methods, apparatus and computer readable medium for handling error correction in a memory are disclosed. In some embodiments, first data is written to the memory, and a value(s) of an operational parameter(s) that is a consequence of the writing of the first data is determined. Second data is read from the memory, and the value(s) of the operational parameter(s) may be used when correcting errors in the second data. In some embodiments, the first data is the same as the second data. The presently-disclosed teachings are applicable to any kind of memory including (i) non-volatile memories such as flash memory, magnetic memory and optical storage and (ii) volatile memory such as SRAM or DRAM.
1. A method for handling error correction, the method comprising
writing first data to a memory;
measuring reliability of the writing of the first data;
determining a value for an operational parameter based on the measured reliability of the writing;
subsequent to the writing and to the determining, reading second data from the memory;
selecting a decoder based on the value for the operational parameter associated with the measured reliability of the writing; and
correcting errors in the second data utilizing the selected decoder.
2. The method of claim 1 wherein the memory is a flash memory.
3. The method of claim 1 wherein the first data are written to and the second data are read from a same set of one or more memory cells.
4. The method of claim 1 wherein:
the first data are written to a first set of one or more memory cells;
the second data are read from a second set of one or more memory cells the second set being different from the first set; and
the correcting of errors of the second data being effected if at least one of a first set condition, a second set condition and a third set condition is true, and wherein the set conditions are defined as follows:
according to the first set condition, a subset of the first set of memory cells and a subset of the second set of memory cells co-reside on a common die;
according to the second set condition, a subset of the first set of memory cells and a subset of the second set of memory cells co-reside in a common memory cell block; and
according to the third set condition, a subset of the first set of memory cells and a subset of the second set of memory cells co-reside on a common wordline.
5. The method of claim 1 wherein the value for the operational parameter is based on a number of bits left in incorrect state at an end of the writing of the first data.
6. The method of claim 1 wherein the correcting of errors in the second data includes selecting a decoding bus width size in accordance with the value for the operational parameter.
7. The method of claim 1 wherein the selecting the decoder includes at least one of:
choosing one of a first decoder or a second decoder in accordance with the value for the operational parameter and correcting errors using the chosen decoder; and
choosing one of a first mode of a decoder or a second mode of the decoder in accordance with the value for the operational parameter and correcting errors using the chosen mode of the decoder.
8. The method of claim 1 wherein the correcting of errors includes at least one of:
deciding whether to attempt to correct errors using a lighter-weight decoder or to attempt to correct errors using a heavier-weight decoder that is heavier than the lighter-weight decoder;
deciding whether to attempt to correct errors using a faster decoder or to attempt to correct errors using a slower decoder that is slower than the faster decoder;
deciding whether to attempt to correct errors using a lighter-weight mode of a particular decoder or to attempt to correct errors using a heavier-weight mode of the particular decoder that is heavier than the lighter weight mode; and
deciding whether to attempt to correct errors using a faster mode of a particular decoder or to attempt to correct errors using a slower mode of the particular decoder that is slower than the faster mode.
9. The method of claim 1 wherein the correcting of errors in the second data includes determining, in accordance with the value for the operational parameter, one or more bit-probability values for the second data.
10. The method of claim 1 wherein the value of the determined operational parameter is based on a number of programming iterations used in the writing of the first data.
11. The method of claim 1 wherein the value of the determined operational parameter is based on a time required for the writing of the first data.
12. The method of claim 1 wherein:
the first data are written to a first set of one or more memory cells; and
the second data are read from a second set of one or more memory cells, the second set being different from the first set.
13. The method of claim 12 wherein the method is carried out such that at least one of a first set condition, a second set condition, a third set condition, and a fourth set condition is true, and wherein the set conditions are defined as follows:
according to the first set condition, the first set of one or more memory cells and the second set of one or more memory cells include at least one common memory cell;
according to the second set condition, the first set of memory cells and the second set of memory cell sets are disjoint sets;
according to the third set condition, the first set of memory cells is a subset of the second set of memory cells; and
according to the fourth set condition, the second set of memory cells is a subset of the first set of memory cells.
14. A data storage device comprising:
a memory; and
a controller operative to:
write first data to the memory;
measure reliability of the write of the first data;
determine a value for an operational parameter based on the measured reliability of the write;
subsequent to the writing and to the determining, read second data from the memory;
select a decoder based on the value for the operational parameter associated with the measured reliability of the write; and
correct errors in the second data utilizing the selected decoder.
15. The device of claim 14 wherein the memory is a flash memory.
16. The device of claim 14 wherein the memory includes a plurality of memory cells and the controller is operative to write the first data and read the second data from the same set of one or more of the memory cells.
17. The device of claim 14 wherein the memory includes a plurality of memory cells and the controller is operative:
to write the first data to a first set of one or more of the memory cells;
to read the second data from a second set of one or more of the memory cells the second set being different from the first set; and
to effect the correcting of the second data if at least one of a first set condition, a second set condition and a third set condition is true, and wherein the set conditions are defined as follows:
according to the first set condition, a subset of the first set of memory cells and a subset of the second set of memory cells co-reside on a common die;
according to the second set condition, a subset of the first set of memory cells and a subset of the second set of memory cells co-reside in a common memory cell block; and
according to the third set condition, a subset of the first set of memory cells and a subset of the second set of memory cells co-reside on a common wordline.
18. The device of claim 14 wherein the determined operational parameter value describes at least one of a number of bits left in incorrect state at the end of the writing of the first data; a number of programming iterations used in the writing of the first data; or a time required for the writing of the first data.
19. The device of claim 14 wherein the controller is operative such that the correcting of errors in the second data includes selecting a decoding bus width size in accordance with the value for the operational parameter.
20. The device of claim 14 wherein the controller is operative such that the selecting the decoder includes effecting at least one of:
choosing one of a first decoder or a second decoder in accordance with the value for the operational parameter and correcting errors using the chosen decoder; and
choosing one of a first mode of a decoder or a second mode of the decoder in accordance with the value for the operational parameter and correcting errors using the chosen mode of the decoder.
21. The device of claim 14 wherein the controller is operative such that the correcting of errors according to the determined operational parameter value includes at least one of:
deciding whether to attempt to correct errors using a lighter-weight decoder or to attempt to correct errors using a heavier-weight decoder that is heavier than the lighter-weight decoder;
deciding whether to attempt to correct errors using a faster decoder or to attempt to correct errors using a slower decoder that is slower than the faster decoder;
deciding whether to attempt to correct errors using a lighter-weight mode of a particular decoder or to attempt to correct errors using a heavier-weight mode of the particular decoder that is heavier than the lighter weight mode; and
deciding whether to attempt to correct errors using a faster mode of a particular decoder or to attempt to correct errors using a slower mode of the particular decoder that is slower than the faster mode.
22. The device of claim 14 wherein the controller is operative such that the correcting of errors includes determining, in accordance with the value for the operational parameter, one or more bit-probability values for the second data.
23. The device of claim 14 wherein the memory includes a plurality of memory cells and the controller is operative:
to write the first data to a first set of one or more of the memory cells; and
to read the second data from a second set of one or more of the memory cells, the second set being different from the first set.
24. The device of claim 23 wherein the controller is operative such that at least one of a first set condition, a second set condition, a third set condition, and a fourth set condition is true, and wherein the set conditions are defined as follows.
according to the first set condition, the first set of one or more memory cells and the second set of one or more memory cells include at least one common memory cell;
according to the second set condition, the first set of memory cells and the second set of memory cell sets are disjoint sets;
according to the third set condition, the first set of memory cells is a subset of the second set of memory cells; and
according to the fourth set condition, the second set of memory cells is a subset of the first set of memory cells.
25. A host device comprising:
a host-side storage;
a host-side processor;
a host-side interface for inter-device coupling with a memory device; and
driver code residing in the host-side storage, wherein execution of the driver code by the host-side processor is operative to:
write first data to the memory;
measure reliability of the write of the first data;
determine a value for an operational parameter based on the measured reliability of the write;
subsequent to the writing and to the determining, read second data from the memory;
select a decoder based on the value for the operational parameter associated with the measured reliability of the write; and
handle error correction of the second data utilizing the selected decoder.
26. The host device of claim 25 wherein the driver code is operative such that handling of error correction includes issuing a command, via the host-side interface, to handle the error correction of the second data according to the value for the operational parameter.
27. The host device of claim 25 wherein the driver code is operative such that the handling of error correction includes correcting errors, on the host side, in the second data according to the value for the operational parameter.
28. A computer program embedded in a non-transitory computer-readable storage medium, when executed by one or more processors for handling error correction for a memory, the computer program code being operable to:
write first data to the memory;
measure reliability of the write of the first data;
determine a value for an operational parameter based on the measured reliability of the write;
subsequent to the writing and to the determining, read second data from the memory;
select a decoder based on the value for the operational parameter associated with the measured reliability of the write; and
correct errors in the second data utilizing the selected decoder.
29. A controller for a memory, the memory including a plurality of memory cells, the controller comprising:
circuitry that is operative to:
write first data to the memory;
measure reliability of the write of the first data
determine a value for an operational parameter based on the measured reliability of the write;
subsequent to the writing and to the determining, read second data from the memory;
select a decoder based on the value for the operational parameter associated with the measured reliability of the write; and
correct errors in the second data utilizing the selected decoder.