Semiconductor device
View Patent ↗The semiconductor device of the present invention has a body layer of a P-type impurity region formed on an N − layer of an N-type impurity region. A plurality of trenches is formed through the body layer from the main surface thereof. A gate insulating film and a gate electrode are formed in each trench. A contact layer of a P-type impurity region and an emitter layer of an N-type impurity region are formed on the main surface of the body layer. A plurality of floating ring layers of P-type impurity regions is formed on the main surface of the N − layer, being spaced apart from the body layer. A well layer of an N-type impurity region is formed between the body layer and N − layer in an area contained in the body layer in plane view.
1. A semiconductor device including an insulated gate bipolar transistor, comprising:
a first semiconductor layer of a first conductivity type impurity region;
a second semiconductor layer of a second conductivity type impurity region formed on the first semiconductor layer;
a plurality of trench formed regions formed through the second semiconductor layer from the main surface thereof;
a gate insulating film and a gate electrode formed within the respective trench formed regions;
a contact layer of the second conductivity type impurity region formed on the main surface of the second semiconductor layer;
an emitter layer of the first conductivity type impurity region formed on the main surface of the second semiconductor layer;
a plurality of third semiconductor layers of the second conductivity type impurity region which is formed spaced apart from the second semiconductor layer on the main surface of the first semiconductor layer; and
a fourth semiconductor layer of the first conductivity type impurity region formed between the second semiconductor layer and the first semiconductor layer within an area contained in the second semiconductor layer in plane view, formed only inside an edge of the second semiconductor layer in plane view, and formed continuously across a plurality of the trench formed regions.
2. A semiconductor device according to claim 1 , wherein the fourth semiconductor layer is formed inside the outermost edge of the plurality of the trench formed regions in plane view.
3. A semiconductor device according to claim 1 , further comprising:
a fifth semiconductor layer of the first conductivity type impurity region containing the third semiconductor layer,
wherein an impurity concentration of the fifth semiconductor layer is higher than that of the first semiconductor layer.
4. A semiconductor device according to claim 2 , further comprising:
a fifth semiconductor layer of the first conductivity type impurity region containing the third semiconductor layer,
wherein an impurity concentration of the fifth semiconductor layer is higher than that of the first semiconductor layer.
5. A semiconductor device according to claim 3 , wherein the fifth semiconductor layer is individually formed to the each third semiconductor layer.
6. A semiconductor device according to claim 4 , wherein the fifth semiconductor layer is individually formed to the each third semiconductor layer.
7. A semiconductor device according to claim 5 , wherein
in plane view, a pair of the fifth semiconductor layers on both sides of the third semiconductor layer is disposed in a state that a width of the fifth semiconductor layer on the side away from the second semiconductor layer is larger than a width of the fifth semiconductor layer on the side closer to the second semiconductor layer.
8. A semiconductor device according to claim 6 , wherein
in plane view, a pair of the fifth semiconductor layers on both sides of the third semiconductor layer is disposed in a state that a width of the fifth semiconductor layer on the side away from the second semiconductor layer is larger than a width of the fifth semiconductor layer on the side closer to the second semiconductor layer.
9. A semiconductor device according to claim 3 , wherein
in plane view, a width of the fifth semiconductor layer on either side of one of the third semiconductor layers is larger than a width of fifth semiconductor layer on either side of another third semiconductor layer closer to the second semiconductor layer.
10. A semiconductor device according to claim 4 , wherein
in plane view, a width of the fifth semiconductor layer on either side of one of the third semiconductor layers is larger than a width of fifth semiconductor layer on either side of another third semiconductor layer closer to the second semiconductor layer.
11. A semiconductor device according to claim 5 , wherein
in plane view, a width of the fifth semiconductor layer on either side of one of the third semiconductor layers is larger than a width of fifth semiconductor layer on either side of another third semiconductor layer closer to the second semiconductor layer.
12. A semiconductor device according to claim 6 , wherein
in plane view, a width of the fifth semiconductor layer on either side of one of the third semiconductor layers is larger than a width of fifth semiconductor layer on either side of another third semiconductor layer closer to the second semiconductor layer.
13. A semiconductor device according to claim 7 , wherein
in plane view, a width of the fifth semiconductor layer on either side of one of the third semiconductor layers is larger than a width of fifth semiconductor layer on either side of another third semiconductor layer closer to the second semiconductor layer.
14. A semiconductor device according to claim 8 , wherein
in plane view, a width of the fifth semiconductor layer on either side of one of the third semiconductor layers is larger than a width of fifth semiconductor layer on either side of another third semiconductor layer closer to the second semiconductor layer.
15. A semiconductor device according to claim 1 , wherein the second semiconductor layer and the third semiconductor layers are formed in the same process of forming impurity regions at the same time.
16. A semiconductor device according to claim 2 , wherein the second semiconductor layer and the third semiconductor layers are formed in the same process of forming impurity regions at the same time.
17. A semiconductor device according to claim 3 , wherein the fourth semiconductor layer and the fifth semiconductor layers are formed in the same process of forming impurity regions at the same time.
18. A semiconductor device according to claim 4 , wherein the fourth semiconductor layer and the fifth semiconductor layers are formed in the same process of forming impurity regions at the same time.