Dynamic gate drive voltage adjustment

1. A DC-DC buck converter comprising:

an input terminal;

an output terminal for supplying an output current to a load;

a reference voltage terminal;

an inductor coupled to the output terminal;

a high-side power FET having a current path coupled in series between the input terminal and the inductor;

a low-side power FET having a current path coupled between the reference voltage terminal and node between the high-side power FET and the inductor;

a pulse width modulation controller coupled to receive a feedback signal from the output terminal, for providing pulse width modulated signals; and

a gate driver circuit coupled to receive the pulse width modulated signals from the pulse width modulation (PWM) controller and, responsive thereto, to apply pulse width modulated drive signals to gates of the high-side and low-side power FETs, wherein the gate driver circuit supplies the drive signals to the gates of the power FETs at a variable voltage level adjusted in response to at least the output current, in order to substantially minimize the power dissipation of the gate driver circuit;

a gate drive voltage controller that is coupled to receive signals that are representative of an input voltage at the input terminal, an output voltage at the output terminal, an input current at the input terminal, and the output current, wherein the gate drive voltage controller generates an adjustment signal at least in part in response to the signals that are representative of the input voltage, the output voltage, the input current, and the output current; and

a voltage regulator that is coupled to the gate drive voltage controller so as to receive the adjustment signal and that is coupled to the gate driver circuit so as to provide an adjusted gate drive voltage to the gate driver circuit based at least in part on the adjustment signal.

2. The converter of claim 1 , wherein the gate drive voltage controller computes input power and output power and supplies the adjustment signal to the voltage regulator so as to substantially minimize the difference between the input power and the output power.

3. The converter of claim 2 , wherein the gate drive voltage controller is implemented by at least one of a microcontroller, a digital signal processor, an application specific integrated circuit, and a field programmable gate array.

4. The converter of claim 1 , wherein the gate drive voltage controller uses a look-up table to determine the substantially optimum gate drive voltage.

5. The converter of claim 4 , wherein the gate drive voltage controller is configured for operation in a learn mode to generate the look-up table.

6. An apparatus comprising:

an input terminal;

a feedback terminal;

a first switch that is coupled to the input terminal;

a second switch that is coupled to the first switch at a switching node;

a driver that is coupled to the first and second switches, wherein the driver actuates and deactuates each of the first and second switches;

a PWM controller that is coupled to the feedback terminal and to the driver, wherein the PWM controller provide pulse width modulated signals to the driver;

a gate drive voltage controller that is coupled to receive signals that are representative of an input voltage at the input terminal, the output voltage at an output terminal, an input current at the input terminal, and the output current at the output terminal, wherein the gate drive voltage controller generates an adjustment signal at least in part in response to the signals that are representative of the input voltage, the output voltage, the input current, and the output current; and

a voltage regulator that is coupled to the gate drive voltage controller so as to receive the adjustment signal and that is coupled to the driver so as to provide an adjusted gate drive voltage to the driver based at least in part on the adjustment signal.

7. The apparatus of claim 6 , wherein the first switch is an NMOS FET that is coupled to the input terminal at its drain, the switching node at its source and the driver at its gate.

8. The apparatus of claim 6 , wherein the second switch is an NMOS FET that is coupled to the switching node at its drain and the driver at its gate.

9. The apparatus of claim 6 , wherein the gate drive voltage controller computes input power and output power and supplies the adjustment signal to the voltage regulator so as to substantially minimize the difference between the input power and the output power.

10. The apparatus of claim 9 , wherein the gate drive voltage controller is implemented by at least one of a microcontroller, a digital signal processor, an application specific integrated circuit, and a field programmable gate array.

11. The apparatus of claim 6 , wherein the gate drive voltage controller uses a look-up table to determine the substantially optimum gate drive voltage.

12. The apparatus of claim 11 , wherein the gate drive voltage controller is configured for operation in a learn mode to generate the look-up table.