IP Library Granted Patent US 8,031,952
Granted Patent B2
US 8,031,952 · App. 12/106,729 · Granted Oct 4, 2011

Method and apparatus for optimizing memory usage in image processing

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Quick Facts
Patent No.
US 8,031,952
App. No.
12/106,729
Granted
Oct 4, 2011
Kind
B2
Abstract

A method and digital camera avoiding the use of delay lines for block processing within the camera, such as compressing images, demosaicing, or the like. Processing is done for a block comprising a single newly received line, together with previously acquired information. In one preferred embodiment, the block processing is performed for the single line using previous lines as retrieved from the results of previous processing. In another embodiment, the processing results for the current block are determined by the processing results of the previous block together with the newly received line. Saving delay lines provides for lower memory requirements, and enables the production of smaller and lower cost cameras.

Claims (37)

1. A method for processing a pixel block, comprising:

using a processor to perform the following:

receiving data related to at least one previously captured image line, the data differing from the at least one previously captured image line;

receiving at least one captured pixel, the at least one captured pixel belonging to at least one captured image line; and

processing the at least one captured pixel and the data related to the at least one previously captured image line to obtain a processed block result, wherein the processing comprises performing JPEG compression, and wherein JPEG coefficients are determined by rotating previous JPEG coefficients, subtracting a normalized value of an outdated pixel, and adding a normalized value of the at least one captured pixel.

2. The method of claim 1 wherein the pixel block comprises a rectangular pixel block.

3. The method of claim 1 further comprising deprocessing the processed block results to obtain at least one image line.

4. The method of claim 3 wherein the deprocessing comprises performing one or more of the following: JPEG decompression; JPEG 2000 decompression; wavelet decompression; MPEG decompression; and mosaicing.

5. The method of claim 1 wherein the data related to the at least one previously captured image line is a reconstruction of the at least one previously captured image line.

6. The method of claim 1 wherein the data related to the at least one previously captured image line is an estimated reconstruction of the at least one previously captured image line.

7. The method of claim 1 wherein the data related to the at least one previously captured image line comprises a block processing result of an estimation of the at least one previously captured image line.

8. The method of claim 1 further comprising storing the block processing results.

9. The method of claim 1 further comprising correcting an error in the processed block result.

10. The method of claim 1 wherein the processing comprises performing one or more of the following: JPEG compression; JPEG 2000 compression; wavelet compression; MPEG compression; and demosaicing.

11. The method of claim 1 wherein the method is performed in an image processing device.

12. The method of claim 1 wherein the method is performed in a digital camera.

13. A method for processing a pixel block using a reduced number of delay lines, comprising:

using a processor to perform the following:

receiving data related to previously captured at least one image line;

receiving at least one captured pixel, the at least one captured pixel belonging to a single captured image line; and

processing the at least one captured pixel and the data related to the previously captured at least one image line to obtain a processed block result, wherein the processing comprises performing JPEG compression, and wherein JPEG coefficients are determined by rotating previous JPEG coefficients, subtracting a normalized value of an outdated pixel, and adding a normalized value of the at least one captured pixel.

14. An image processing device for processing a pixel block, the device comprising:

a memory unit comprising a delay line that stores at least one image line;

a processor that executes a processing engine that processes a pixel block comprising the at least one image line, from the delay line and from data related to at least one previously captured image line, to obtain a processed block result, wherein the processing engine performs JPEG compression, and wherein JPEG coefficients are determined by rotating previous JPEG coefficients, subtracting a normalized value of an outdated pixel and adding a normalized value of the at least one captured pixel.

15. The image processing device of claim 14 wherein the pixel block comprises a rectangular pixel block.

16. The image processing device of claim 14 wherein the processor further executes a deprocessing engine that deprocesses the processed block results to obtain an estimation to the at least one previously captured image line.

17. The image processing device of claim 16 wherein the deprocessing engine performs one or more of the following: JPEG decompression; JPEG 2000 decompression; wavelet decompression; MPEG decompression; and mosaicing.

18. The image processing device of claim 14 wherein the data related to previously captured at least one image line is a reconstruction of the at least one image line.

19. The image processing device of claim 14 wherein the data related to previously captured at least one image line is an estimated reconstruction of the at least one image line.

20. The image processing device of claim 14 wherein the data related to the previously captured at least one image line comprises a block processing result of an estimation of the at least one previously captured image line.

21. The image processing device of claim 14 further comprising a storage device that stores the block processing results.

22. The image processing device of claim 14 wherein the processor further executes error detection and correction in the at least one image line.

23. The image processing device of claim 14 wherein the processing engine performs one or more of the following: JPEG compression; JPEG 2000 compression; wavelet compression; MPEG compression; and demosaicing.

24. A non-transitory computer readable storage medium containing a set of computer instructions the set of computer instructions comprising:

receiving data related to at least one previously captured image line, the data differing from the previously captured at least one image line;

receiving at least one captured pixel, the at least one captured pixel belonging to at least one captured image lines; and

processing the at least one captured pixel and the data related to the at least one previously captured image line to obtain a processed block result, wherein the processing comprises performing JPEG compression, and wherein JPEG coefficients are determined by rotating previous JPEG coefficients, subtracting a normalized value of an outdated pixel, and adding a normalized value of the at least one captured pixel.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE PROPERTY NUMBERS PREVIOUSLY RECORDED AT REEL: 47630 FRAME: 344. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 21, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0267 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 9/5/2018 PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0687. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0344 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0687 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2011
From: SIGHTIC VISTA, LTD.
To: BROADCOM CORPORATION
Reel/Frame 026836/0013 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 21, 2008
From: VITSNUDEL, ILIA
To: SIGHTIC VISTA LTD.
Reel/Frame 020833/0632 →