LOW-POWER SENSE AMPLIFIER
In one embodiment, a sense amplifier for sensing a binary state of a memory cell coupled to a bit line and a complementary bit line and for writing a binary state into the memory cell is provided. The sense amplifier includes: a first pair of switches including a first switch coupled to a node on the bit line and a second switch coupled to a node on the complementary bit line; a signal detector having a first input terminal coupled to the first switch and a second input terminal coupled to the second switch, the signal detector configured to sense voltages on the bit line and the complementary bit line through the first pair of switches during a read operation; a second pair of switches, wherein a first switch in the second pair couples between the node on the bit line and ground and is responsive to a data signal to be written to the memory cell and a second switch couples between the node on the complementary bit line and ground and is responsive to a complementary data signal to be written to the memory cell, wherein if either the data signal or the complementary data signal is true, a corresponding bit line is grounded so as to force the binary state of memory cell into an appropriate value during a write operation; and wherein the first pair of switches are controlled such that they turn on during a read operation while the signal detector determines the binary state of the memory cell, the first pair of switches being off during the write operation whereby a capacitance presented to the bit line and the complementary bit line by the sense amplifier is lower during the write operation than during the read operation.
1 . A sense amplifier for sensing a binary state of a memory cell coupled to a bit line and a complementary bit line and for writing a binary state into the memory cell, comprising:
a first pair of switches including a first switch coupled to a node on the bit line and a second switch coupled to a node on the complementary bit line;
a signal detector having a first input terminal coupled to the first switch and a second input terminal coupled to the second switch, the signal detector configured to sense voltages on the bit line and the complementary bit line through the first pair of switches during a read operation;
a second pair of switches, wherein a first switch in the second pair couples between the node on the bit line and ground and is responsive to a data signal to be written to the memory cell and a second switch couples between the node on the complementary bit line and ground and is responsive to a complementary data signal to be written to the memory cell, wherein if either the data signal or the complementary data signal is true, a corresponding bit line is grounded so as to force the binary state of memory cell into an appropriate value during a write operation; and
wherein the first pair of switches are controlled such that they turn on during a read operation while the signal detector determines the binary state of the memory cell, the first pair of switches being off during the write operation whereby a capacitance presented to the bit line and the complementary bit line by the sense amplifier is lower during the write operation than during the read operation.
2 . The sense amplifier of claim 1 , wherein the sense amplifier is a static random access memory (SRAM) sense amplifier.
3 . The SRAM sense amplifier of claim 2 , wherein the signal detector comprises a cross-coupled pair of inverters.
4 . The SRAM sense amplifier of claim 2 , wherein the SRAM sense amplifier is implemented using a CMOS manufacturing process.
5 . The SRAM sense amplifier of claim 2 , further comprising:
a third switch coupled in series with the first switch in the second pair of switches, the third switch being controlled by a write enable signal; and
a fourth switch coupled in series with the second switch in the second pair of switches, the fourth switch being controlled by the write enable signal.
6 . The SRAM sense amplifier of claim 5 , wherein the first pair of switches comprise PMOS transistors having their gates driven by an active low read enable signal.
7 . The SRAM sense amplifier of claim 6 , wherein the second pair of switches and the third and fourth switches comprise NMOS transistors.
8 . The SRAM sense amplifier of claim 6 , further comprising an SRAM array including the memory cell.
9 . A sense amplifier for sensing a binary state of a memory cell coupled to a bit line and a complementary bit line and for writing a binary state into the memory cell, comprising:
a first means for sensing the binary state of the memory cell during a read operation through a coupling to the bit line and the complementary bit line;
a second means for coupling the first means to the bit line and the complementary bit line during a read operation and for isolating the first means from the bit line and the complementary bit line during a write operation; and
a third means for selectively coupling either the bit line or the complementary bit line to ground during the write operation, whereby a capacitance presented by the sense amplifier to the bit line and the complementary bit line during the write operation is less than a capacitance presented by the sense amplifier to the bit line and the complementary bit line during the read operation.
10 . The sense amplifier of claim 9 , wherein the sense amplifier is a static random access memory (SRAM) sense amplifier.
11 . The SRAM sense amplifier of claim 10 , wherein the first means comprises a cross-coupled pair of inverters.
12 . The SRAM sense amplifier of claim 11 , wherein the SRAM sense amplifier is implemented using a CMOS manufacturing process.
13 . The SRAM sense amplifier of claim 10 , wherein the second means comprises a first switch between a first input of the first means and the bit line and a second switch between a second input of the first means and the complementary bit line.
14 . The SRAM sense amplifier of claim 13 , wherein the first and second switches comprise PMOS transistors having their gates driven by an active low read enable signal.
15 . The SRAM sense amplifier of claim 10 , wherein the third means comprises:
a first switch that couples between the bit line and ground; and
a second switch that couples between ground and the complementary bit line, the first and second being controlled such that just one of the switches turns on during the write operation so as to force the binary state of memory cell into an appropriate value during the write operation.
16 . The SRAM sense amplifier of claim 15 , wherein the first switch is controlled by a data signal and the second switch is controlled by a complementary data signal.
17 . The SRAM sense amplifier of claim 15 , further comprising:
a third switch coupled in series with the first switch, the third switch being controlled by a write enable signal; and
a fourth switch coupled in series with the second switch, the fourth switch being controlled by the write enable signal.
18 . A method of sensing a binary content of a static random access memory (SRAM) cell using a signal detector during a read operation and writing to the SRAM cell during a write operation, the signal detector detecting the binary content through a bit line and a complementary bit line, the method comprising:
isolating the signal detector from the bit line and the complementary bit line during the write operation;
if a true signal is to be stored in the memory cell while the signal detector is isolated, grounding the bit line;
if a false signal is to be stored in the memory cell while the signal detector is isolated, grounding the complementary bit line; and
during the read operation, coupling the signal detector to the bit line and the complementary bit line.
19 . The method of claim 18 , wherein the coupling the signal detector to the bit line act occurs responsive to a read enable signal.
20 . The method of claim 19 , wherein the read enable signal is an active low read enable signal.