IP Library Granted Patent US 8,063,433
Granted Patent B2
US 8,063,433 · App. 12/109,340 · Granted Nov 22, 2011

Nonvolatile semiconductor memory device

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Quick Facts
Patent No.
US 8,063,433
App. No.
12/109,340
Granted
Nov 22, 2011
Kind
B2
Abstract

A memory cell includes an ONO film composed of a stacked film of a silicon nitride film SIN which is a charge trapping portion and oxide films BOTOX and TOPOX positioned under and over the silicon nitride film, a memory gate electrode MG over the ONO film, a source region MS, and a drain region MD, and program or erase is performed by hot carrier injection in the memory cell. In the memory cell, a total concentration of N—H bonds and Si—H bonds contained in the silicon nitride film SIN is made to be 5×10 20 cm −3 or less.

Claims (36)

1. A nonvolatile semiconductor memory device comprising:

a pair of source and drain regions formed in a semiconductor substrate;

a first gate electrode formed over a region of the semiconductor substrate between the source and drain regions; and

a charge trapping portion formed between a surface of the semiconductor substrate and the first gate electrode,

wherein the charge trapping portion includes a first nitride film and a second nitride film,

wherein, in the first nitride film, a total concentration of N—H bonds and Si—H bonds is 5×10 20 cm −3 or less,

wherein the second nitride film is formed directly on the first nitride film, and

wherein a program or erase is performed by hot carrier injection into the charge trapping portion.

2. The nonvolatile semiconductor memory device according to claim 1 ,

wherein a film thickness of the first nitride film is 3 nm or less.

3. The nonvolatile semiconductor memory device according to claim 1 ,

wherein the charge trapping portion further includes a third nitride film,

the third nitride film is formed directly on the second nitride film, and

the third nitride film is a nitride film in which a total concentration of the N—H bonds and Si—H bonds is 5×10 20 cm −3 or less.

4. The nonvolatile semiconductor memory device according to claim 3 ,

wherein the film thickness of the third nitride film is 3 nm or less.

5. The nonvolatile semiconductor memory device according to claim 1 , further comprising a second gate electrode formed over the region of the semiconductor substrate between the source and drain regions.

6. The nonvolatile semiconductor memory device according to claim 1 ,

wherein the first nitride film is formed by depositing a nitride film by a chemical vapor deposition method and then being nitrided by nitrogen in a plasma state.

7. The nonvolatile semiconductor memory device according to claim 1 ,

wherein the first nitride film is deposited and formed by a sputtering method.

8. The nonvolatile semiconductor memory device according to claim 1 ,

wherein the first nitride film is deposited and formed by an atomic layer deposition method in which SiCl 4 or Si 2 Cl 6 and a nitrogen gas in a plasma state are alternately exposed to the film.

9. The nonvolatile semiconductor memory device according to claim 1 ,

wherein an oxide film is further disposed between the first nitride film and the surface of the semiconductor substrate, and

the first nitride film is formed with a part of the oxide film being subjected to plasma nitridation.

10. The nonvolatile semiconductor memory device according to claim 1 ,

wherein the first nitride film is an oxynitride film.

11. The nonvolatile semiconductor memory device according to claim 1 ,

wherein the nitride film is a silicon nitride film, and when a composition of the silicon nitride film is Si 3+x N 4 , X is 0.05 or less.

12. The nonvolatile semiconductor memory device according to claim 1 , further comprising

an additional nitride film that covers an entirety of the surface of the semiconductor substrate in the memory region except for a contact part of the semiconductor substrate.

13. The nonvolatile semiconductor memory device according to claim 1 , further comprising an oxide film formed between the surface of the semiconductor substrate and the charge trapping portion,

wherein a bond between a halogen element and a silicon element is present in an interface between the oxide film and the semiconductor substrate or in the oxide film.

14. The nonvolatile semiconductor memory device according to claim 13 ,

wherein the halogen element is fluorine.

Assignments (4)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
MERGER Recorded Sep 1, 2010
From: RENESAS TECHNOLOGY CORP.
To: NEC ELECTRRONICS CORPORATION
Reel/Frame 024933/0869 →
CHANGE OF NAME Recorded Sep 1, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024953/0404 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2008
From: ISHIMARU, TETSUYA; SHIMAMOTO, YASUHIRO; MINE, TOSHIYUKI; AOKI, YASUNOBU; TOBA, KOICHI; YASUI, KAN
To: RENESAS TECHNOLOGY CORP.
Reel/Frame 020854/0504 →