INTEGRATED CIRCUIT CHIP WITH IMPROVED ARRAY STABILITY
A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g., in the data path and in non-critical logic, are tailored for lower gate and subthreshold leakage. Normal base FETs have a base threshold and tailored FETs have a threshold above. In a multi-supply chip, circuits with tailored FETs are powered by an increased supply voltage.
1 . An integrated circuit (IC) chip comprising:
a plurality of logic paths, ones of said plurality of logic paths being identified as critical paths, logic circuits in said critical paths being of devices having a stated base design characteristic; and
logic circuits in remaining ones of said plurality of logic paths being formed of tailored said devices, said tailored devices exhibiting less leakage than devices having said stated base design characteristic.
2 . An IC chip as in claim 1 , wherein said devices are field effect transistors (FETs).
3 . An IC chip as in claim 2 , wherein said stated base characteristic is a stated design gate dielectric thickness and said tailored FETs have a thicker gate oxide than said stated design gate dielectric thickness.
4 . An IC chip as in claim 2 , wherein said stated base characteristic is a channel dopant characteristic and said tailored FETs have a subthreshold leakage reduction channel implant.
5 . An IC chip as in claim 2 , wherein said stated base characteristic is gate oxide and said tailored FETs have a high k gate dielectric material.
6 . An IC chip as in claim 2 , wherein said stated base characteristic is a stated design gate dielectric thickness and a channel dopant characteristic and said tailored FETs have a subthreshold leakage reduction channel implant and a thicker gate oxide than a stated design gate oxide thickness.
7 . An IC chip as in claim 6 , wherein said stated base characteristic is a base threshold voltage (V T ) and said tailored FETs have an increased threshold voltage (V T+ ) that is greater than said base V T .
8 . An IC chip as in claim 7 , further comprising:
a base voltage source connected to a base supply line and supplying a base voltage to said critical paths; and
an increased voltage source supplying an increased voltage to said logic circuits in said remaining ones, wherein said tailored FETs exhibit less leakage at said increased voltage than FETs having said stated base design characteristic at said base voltage.
9 . An IC chip as in claim 8 , wherein said increased voltage (V dd+ ) exceeds said base voltage (V dd ) at least by the difference between the base V T and said increased V T+ , i.e., V dd+ −V dd >|V T+ −V T |.
10 . An IC chip as in claim 9 , further comprising an array of storage cells and support circuits for said array, said storage cells and support circuits including tailored FETs and connected to said increased voltage.
11 . An integrated circuit (IC) chip comprising:
a base voltage source connected to a base supply line and supplying a base voltage;
a plurality of logic paths, ones of said plurality of logic paths being identified as critical paths, devices in said critical paths having a stated base design characteristic, circuits in said critical paths being connected to said base supply line;
an increased voltage source connected to an increased supply line and supplying an increased voltage, said increased voltage being above said base voltage; and
ones of said plurality of logic paths not being identified as one of said critical paths, circuits in said ones having tailored said devices and connected to said increased supply line, said tailored devices exhibiting less leakage at said base voltage than devices having said stated base design characteristic.
12 . An IC chip as in claim 11 , wherein said devices are field effect transistors (FETs).
13 . An IC chip as in claim 12 , wherein said tailored FETs exhibit less leakage at said increased voltage than FETs having said stated base design characteristic at said base voltage.
14 . An IC chip as in claim 13 , wherein said stated base characteristic is a stated design gate dielectric thickness and said tailored FETs have a thicker gate oxide than said stated design gate dielectric thickness.
15 . An IC chip as in claim 13 , wherein said stated base characteristic is a channel dopant characteristic and said tailored FETs have a subthreshold leakage reduction channel implant.
16 . An IC chip as in claim 13 , wherein said stated base characteristic is gate oxide and said tailored FETs have a high k gate dielectric material.
17 . An IC chip as in claim 13 , wherein said stated base characteristic is a stated design gate dielectric thickness and a channel dopant characteristic and said tailored FETs have a subthreshold leakage reduction channel implant and a thicker gate oxide than a stated design gate oxide thickness.
18 . An IC chip as in claim 17 , wherein said stated base characteristic is a base threshold voltage (V T ) and said tailored FETs have an increased threshold voltage (V T+ ) that is greater than said base V T .
19 . An IC chip as in claim 18 , wherein said increased voltage (V dd+ ) exceeds said base voltage (V dd ) at least by the difference between the base V T and said increased V T+ , i.e., V dd+ −V dd >|V T+ −V T |.
20 . An IC chip as in claim 19 , further comprising an array of storage cells and support circuits for said array, said storage cells and support circuits including tailored FETs and connected to said increased supply line.