Architecture for local programming of quantum processor elements using latching qubits
View Patent ↗An architecture for a quantum processor may include a set of superconducting flux qubits operated as computation qubits and a set of superconducting flux qubits operated as latching qubits. Latching qubits may include a first closed superconducting loop with serially coupled superconducting inductors, interrupted by a split junction loop with at least two Josephson junctions; and a clock signal input structure configured to couple clock signals to the split junction loop. Flux-based superconducting shift registers may be formed from latching qubits and sets of dummy latching qubits. The devices may include clock lines to clock signals to latch the latching qubits. Thus, latching qubits may be used to program and configure computation qubits in a quantum processor.
1. A superconducting quantum processor comprising:
a plurality of computation qubits, wherein each computation qubit comprises a qubit loop formed by a loop of superconducting material and a compound Josephson junction that interrupts the qubit loop, the compound Josephson junction comprising a closed loop of superconducting material interrupted by at least two Josephson junctions, wherein the qubit loop and the compound Josephson junction form a closed superconducting current path, and wherein each computation qubit is configured to perform at least a portion of a quantum computation;
a plurality of latching qubits, wherein each latching qubit comprises a qubit loop formed by a loop of superconducting material and a compound Josephson junction that interrupts the qubit loop, the compound Josephson junction comprising a closed loop of superconducting material interrupted by at least two Josephson junctions, wherein the qubit loop and the compound Josephson junction form a closed superconducting current path, and wherein each latching qubit is inductively coupled to at least one of a computation qubit and another latching qubit; and
a clock signal input structure configured to couple clock signals to the compound Josephson junction of at least one latching qubit, wherein the clock signal input structure includes at least one superconducting inductor positioned sufficiently proximate the compound Josephson junction of the at least one latching qubit to inductively couple clock signals thereto.
2. The superconducting quantum processor of claim 1 wherein the clock signal input structure is configured to couple clock signals at an adiabatic frequency.
3. The superconducting quantum processor of claim 2 wherein the adiabatic frequency is below 20 GHz.
4. The superconducting quantum processor of claim 1 wherein the plurality of latching qubits includes a set of latching qubits arranged to form a flux-based superconducting shift register, the flux-based superconducting shift register comprising:
a set of administration latching qubits, each of the administration latching qubits coupled to receive administration clock signals and coupled to provide output flux signals to at least one programmable device of the quantum processor;
a first set of dummy latching qubits, each of the dummy latching qubits of the first set of dummy latching qubits coupled to receive first dummy clock signals;
a second set of dummy latching qubits, each of the dummy latching qubits of the second set of dummy latching qubits coupled to receive second dummy clock signals, wherein for each pair of successive ones of the administration latching qubits in the set of administration latching qubits, a respective one of the dummy latching qubits from the first set of latching qubits and a respective one of the dummy latching qubits from the second set of dummy latching qubits are positioned to couple flux between the administration latching qubits of the pair of successive ones of the administration latching qubits;
an administration clock signal line inductively coupled to provide the administration clock signals to the administration latching qubits;
a first dummy clock signal line inductively coupled to provide the first dummy clock signals to the dummy latching qubits of the first set of dummy latching qubits; and
a second dummy clock signal line inductively coupled to provide the second dummy clock signals to the dummy latching qubits of the second set of dummy latching qubits.
5. The superconducting quantum processor of claim 4 , wherein at least one programmable device includes a computation qubit from the plurality of computation qubits.
6. The superconducting quantum processor of claim 5 wherein a coupling between an administration latching qubit and a computation qubit is mediated by a digital-to-analog converter.
7. The superconducting quantum processor of claim 4 wherein the administration clock signals, the first dummy clock signals, and the second dummy clock signals are each operated at an adiabatic frequency.
8. The superconducting quantum processor of claim 4 wherein an input signal is inductively coupled to a first one of the administrative latching qubits and propagation of signals through the flux-based superconducting shift register is governed by the administration clock signals, the first dummy clock signals and the second dummy clock signals.
9. The superconducting quantum processor of claim 4 wherein the latching qubits of the set of administration latching qubits, the first set of dummy latching qubits and the second set of dummy latching qubits are arranged in a line of sequential coupling such that each latching qubit is inductively coupled to at least one other latching qubit and any two administration latching qubits are separated by one of the dummy latching qubits from the first set of dummy latching qubits and one of the dummy latching qubits from the second set of dummy latching qubits.
10. The superconducting quantum processor of claim 4 , wherein the flux-based superconducting shift register further comprises:
at least a third set of dummy latching qubits, each of the dummy latching qubits of the third set of dummy latching qubits coupled to receive third dummy clock signals and positioned such that each of the dummy latching qubits of the third set of dummy latching qubits couple flux signals between respective pairs of dummy latching qubits of the first and the second sets of dummy latching qubits; and
a third dummy clock signal line inductively coupled to provide the third dummy clock signals to the dummy latching qubits of the third set of dummy latching qubits such that there is at least one adiabatic clock signal corresponding to each of the first, the second and the third sets of latching qubits.
11. The superconducting quantum processor of claim 1 wherein the plurality of latching qubits includes a set of latching qubits arranged to form a flux-based superconducting shift register, the flux-based superconducting shift register comprising:
a set of administration latching qubits, each of the administration latching qubits having an output structure that couples flux signals out of the flux-based superconducting shift register;
a number of pairs of ON/OFF coupler latching qubits, each pair of the ON/OFF coupler latching qubits coupling flux signals with a respective one of the administration latching qubits when activated by an activation line; and
a set of dummy latching qubits that couple flux signals between the pairs of the ON/OFF coupler latching qubits.
12. The superconducting quantum processor of claim 11 wherein a first one of the administration latching qubits is inductively coupled to a first one of the ON/OFF coupler latching qubits of a first pair of the ON/OFF coupler latching qubits and the first one of the administration latching qubits is inductively coupled to the second one of the ON/OFF coupler latching qubits of the first pair of the ON/OFF coupler latching qubits.
13. The superconducting quantum processor of claim 12 wherein a first one of the dummy latching qubits is inductively coupled to the second one of the first pair of ON/OFF coupler latching qubits and the first one of the dummy latching qubits is inductively coupled to a first one of the ON/OFF coupler latching qubits of a second pair of the ON/OFF coupler latching qubits.
14. The superconducting quantum processor of claim 11 wherein an output structure of at least one administration latching qubit is coupled to at least one programmable element of the quantum processor.
15. The superconducting quantum processor of claim 14 wherein at least one programmable element includes a computation qubit from the plurality of computation qubits.
16. The superconducting quantum processor of claim 15 wherein the coupling between an administration latching qubit and a computation qubit is mediated by a digital-to-analog converter.
17. The superconducting quantum processor of claim 11 wherein the coupling between any two of the administration latching qubits is sequentially mediated by at least two ON/OFF coupler latching qubits, and the coupling between any two ON/OFF coupler latching qubits is mediated by at least one dummy latching qubit.
18. The superconducting quantum processor of claim 17 wherein propagation of an input signal through the flux-based superconducting shift register is governed by the ON/OFF coupler latching qubits.