IP Library Granted Patent US 8,176,402
Granted Patent B2
US 8,176,402 · App. 12/110,064 · Granted May 8, 2012

Decoding apparatus, decoding method, and decoding program

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Quick Facts
Patent No.
US 8,176,402
App. No.
12/110,064
Granted
May 8, 2012
Kind
B2
Abstract

A decoding apparatus includes a memory and a receiving unit and is adapted to decode data in units of codewords each including a parity part. The memory has a storage capacity capable of storing at least data with a length equal to the length of one codeword. The receiving unit receives, as received values, elements of a codeword in a bit-interleaved form, performs bit deinterleaving and parity permutating on the received values, and stores the resultant received values in the memory.

Claims (20)

1. A decoding apparatus adapted to decode data in units of codewords each including a parity part, comprising:

storage means having a storage capacity capable of storing at least data with a length equal to the length of one codeword; and

receiving means for receiving, as received values, elements of a codeword in a bit-interleaved form, simultaneously performing bit deinterleaving and parity permutation on the received values, and storing the resultant received values in the storage means, wherein the bit deinterleaving is performed by writing in the storage means the received values received at immediately adjacent times spaced by a distance corresponding to the number of received values.

2. The decoding apparatus according to claim 1 , wherein the received values corresponding to the elements of the codeword are serially input to the receiving means.

3. The decoding apparatus according to claim 1 , wherein the storage means is configured to store each received value at any specified storage location.

4. The decoding apparatus according to claim 1 , wherein each received value is in the form of a soft value.

5. The decoding apparatus according to claim 1 , wherein the decoding apparatus is adapted to decode an LDPC (Low Density Parity-Check code) code.

6. The decoding apparatus according to claim 1 , wherein the storage means includes a RAM (Random Access Memory).

7. A decoding method for a decoding apparatus adapted to decode data in units of codewords each including a parity part, comprising the steps of, in the decoding apparatus including a memory having a storage capacity capable of storing at least data with a length equal to the length of one codeword,

receiving, as received values, elements of a codeword in a bit-interleaved form;

simultaneously performing bit deinterleaving and parity permutation on the received values, wherein the bit deinterleaving is performed by writing in the storage means the received values received at immediately adjacent times spaced by a distance corresponding to the number of received values; and

storing the resultant received values in the memory.

8. A non-transitory computer-readable medium storing a program executable by a computer to perform a process of decoding data in units of codewords each including a parity part, the process including the steps of,

receiving, as received values, elements of a codeword in a bit-interleaved form;

simultaneously performing bit deinterleaving and parity permutation on the received values, wherein the bit deinterleaving is performed by writing in the storage means the received values received at immediately adjacent times spaced by a distance corresponding to the number of received values; and

storing the resultant received values in a memory disposed in the computer or any other apparatus and having a storage capacity capable of storing at least data with a length equal to the length of one codeword.

9. A decoding apparatus adapted to decode data in units of codewords each including a parity part, comprising:

a memory having a storage capacity capable of storing at least data with a length equal to the length of one codeword; and

a receiving unit adapted to receive, as received values, elements of a codeword in a bit-interleaved form, simultaneously performing bit deinterleaving and parity permutation on the received values, wherein the bit deinterleaving is performed by writing in the storage means the received values received at immediately adjacent times spaced by a distance corresponding to the number of received values, and

storing the resultant received values in the memory.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2016
From: SONY CORPORATION
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 040419/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2008
From: YOKOKAWA, TAKASHI; HIRAYAMA, YUICHI; SHINYA, OSAMU; OKADA, SATOSHI; OGUCHI, KAZUHIRO
To: SONY CORPORATION
Reel/Frame 020864/0401 →